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-- -------------------------------------------------------
-- CI_complex_core
--
-- Purpose of this unit:
-- Speed up operations such as 
-- - image processing 
-- - .. to be completed
-- - .. to be completed
-- For examples see: no address available 
-- Description:
--
--
-- Dependencies:
-- Version: not finished
-- Date:        24/5/2010
-- Created by Philipp Digeser
-- -------------------------------------------------------
-- The following pipe line settings are chosen for the mega functions
-- Multiplier   6
-- Adder                12
-- Divider              18*
-- -------------------------------------------------------
-- *The divider uses 6 pipe line stage, but since it has a 
-- frequency of just clk/3 it is three times slower.
-- Additionally the pipeline can just be fed each third clock
-- this compromise was done to keep a high operation speed 
-- of more than 300 MHz (STRATIX I), current cores are supposed
-- to be faster
-- -------------------------------------------------------
 
-- necessary libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
ENTITY CI_complex_core IS
PORT(
----- general control signals ----------------------------
        signal clk : in std_logic;                                                      -- CPU's master-input clk <required for multi-cycle>
        signal reset : in std_logic;                                            -- CPU's master asynchronous reset <required for multi-cycle>
        signal clk_en: in std_logic;                                            -- Clock-qualifier <required for multi-cycle>
        signal start: in std_logic;                                             -- True when this instr. issues <required for multi-cycle>
        signal done: out std_logic;                                             -- True when instr. completes <required for variable muli-cycle>
 
------ input signals from general purpose registers ------
        signal dataa: in std_logic_vector (31 downto 0);         -- operand A <always required>
        signal datab: in std_logic_vector (31 downto 0);         -- operand B <optional>
        signal result : out std_logic_vector (31 downto 0); -- result <always required>
 
------ for choosing multiple instructions ----------------
        signal n: in std_logic_vector (2 downto 0));             -- N-field selector <required for extended> 
 
END CI_complex_core;
 
ARCHITECTURE core OF CI_complex_core IS
 
        -- for state machine
        type state_type is (s0, s1, s2, s3, s4, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, s32);
        signal state : state_type;
 
        type  clock_type is (clk0, clk1, clk2);
        signal clk_div1 : clock_type;
 
        signal data_A:                  std_logic_vector(31 downto 0);
        signal data_B:                  std_logic_vector(31 downto 0);
        signal data_C:                  std_logic_vector(31 downto 0);
        signal data_D:                  std_logic_vector(31 downto 0);
        signal result_s0:               std_logic_vector(31 downto 0);
 
        signal datapath_dataa:          std_logic_vector(31 downto 0);
        signal datapath_datab:          std_logic_vector(31 downto 0);
        signal datapath_result:         std_logic_vector(31 downto 0);
        signal selected_op:                     std_logic_vector(1 downto 0);
        signal result_buffer:           std_logic_vector(31 downto 0);
        signal result_buffer1:          std_logic_vector(31 downto 0);
 
        constant mult : std_logic_vector := "00";
        constant add_sub : std_logic_vector := "01";
        constant div : std_logic_vector := "10";
 
        signal gl_nan:                  std_logic;
        signal gl_overflow:             std_logic;
        signal gl_underflow:    std_logic;
        signal gl_zero:                 std_logic;
        signal gl_div_by_zero:  std_logic;
        signal gl_n:                    std_logic_vector(2 downto 0);    -- stores the value of n in the first state
 
---------- components -----------------------------------------
 
        component datapath is
        port
        (
                clk :  IN  STD_LOGIC;
                clk_en :  IN  STD_LOGIC;
                aclr :  IN  STD_LOGIC;
                dataa :  IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                datab :  IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                sel :  IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                NaN :  OUT  STD_LOGIC;
                underflow :  OUT  STD_LOGIC;
                zero :  OUT  STD_LOGIC;
                overflow :  OUT  STD_LOGIC;
                division_by_zero :  OUT  STD_LOGIC;
                result :  OUT  STD_LOGIC_VECTOR(31 DOWNTO 0)
        );
        end component;
 
begin
 
 
datapath_inst : datapath PORT MAP(
 
                clk => clk,
                clk_en =>clk_en,
                aclr =>reset,
                dataa =>datapath_dataa,
                datab =>datapath_datab,
                sel =>selected_op,
                NaN =>gl_nan,
                underflow =>gl_underflow,
                zero =>gl_zero,
                overflow =>gl_overflow,
                division_by_zero =>gl_div_by_zero,
                result =>datapath_result
        );
 
------ state machine ----------------------------------------------------
 
        state_machine: process(clk, reset, clk_en) is
        begin
                if (reset='1') then
                        state <= s0;
                elsif (falling_edge(clk) and clk_en = '1') then
                        -- list of modes (n):
                        -- 0: return / get A/C          n = "000" -> ok
                        -- 1: division                          n = "001" -> ok
                        -- 2: multiplication            n = "010" -> ok
                        -- 3: addition                          n = "011" 
                        -- 4: subtraction                       n = "100"
                        -- 5: inverse                           n = "101"
                        -- 6: modulo                            n = "110"
                        -- 7: return errors                     n = "111" -> ok
                        case state is
                                when s0  =>
                                        gl_n    <= n;           -- store n for further processes
                                        if (start = '1') then
                                                if (n = "000") then                             -- n=0 (load & return)
                                                        datapath_dataa  <= dataa;               -- load the first data
                                                        datapath_datab  <= datab;               -- load the second data 
                                                        data_A          <= dataa;               -- and store both data
                                                        data_C          <= datab;
                                                        result          <= result_buffer;       -- return one result
                                                        state           <= s0;                  -- resetstate machine
                                                        done            <= '1';                 -- enable done 
                                                elsif (n<"111") then
                                                        if (n = "100") then                     -- like a subtraction
                                                                datapath_dataa  <= data_A;
                                                                datapath_datab  <= (data_C xor "10000000000000000000000000000000");
                                                        else
                                                                datapath_dataa  <= dataa;
                                                                datapath_datab  <= datab;
                                                        end if;
                                                        data_B          <= dataa;
                                                        data_D          <= datab;
                                                        done            <= '0';
                                                        state           <= s1;
                                                elsif (n = "111") then                  -- RETURN THE ERRORS (Bit 31..27 of result)
                                                        state           <= s0;
                                                        done            <= '1';
                                                        result          <= (gl_nan, gl_overflow, gl_underflow, gl_zero, gl_div_by_zero, others => '0');
                                                else                                                    -- this state does not exist
                                                        state           <= s0;
                                                        done            <= '1';
                                                end if;
                                        end if;
                                when s1  =>
                                        state           <= s2;
                                        if (gl_n = "100") then
                                                datapath_dataa  <= data_B; -- sub
                                                datapath_datab  <= (data_D xor "10000000000000000000000000000000");
                                        else
                                                datapath_dataa  <= data_B; -- mult
                                                datapath_datab  <= data_C;
                                        end if;
                                when s2  =>
                                        state           <= s3;
                                        datapath_dataa  <= data_A; --mult
                                        datapath_datab  <= data_D;
                                when s3  =>
                                        state           <= s4;
                                        datapath_dataa  <= data_C; --mult
                                        datapath_datab  <= data_C;
                                when s4  =>
                                        state           <= s6;
                                        datapath_dataa  <= data_D; --mult
                                        datapath_datab  <= data_D;
                                        selected_op <= mult;
                                when s6  =>
                                        state           <= s7;
                                        datapath_dataa  <= datapath_result;     -- AC addition 
                                when s7  =>
                                        state           <= s8;
                                        if (gl_n = "001") then
                                                datapath_datab  <= datapath_result;     -- BD addition -- first addition starts
                                        elsif (gl_n = "010") then
                                                datapath_datab  <= (datapath_result xor "10000000000000000000000000000000");
                                        end if;
                                when s8  =>
                                        state           <= s9;
                                        if (gl_n = "001") then
                                                datapath_dataa  <= (datapath_result xor "10000000000000000000000000000000");    -- -BC
                                        elsif (gl_n = "010") then
                                                datapath_dataa  <= datapath_result; -- for multiplication we just need BC
                                        end if;
                                when s9  =>
                                        state           <= s10;
                                        datapath_datab <= datapath_result;      -- AD
                                when s10  =>
                                        state           <= s11;
                                        if (gl_n = "001") then --add
                                                datapath_dataa  <= datapath_result;     -- CC
                                        end if;
                                when s11 =>
                                        if (gl_n = "001") then --add
                                                datapath_datab  <= datapath_result;     -- DD
                                        end if;
                                        if (gl_n = "011") then
                                                selected_op <= add_sub;
                                        end if;
                                        state           <= s12;
                                when s12 =>
                                        if (gl_n = "011") then
                                                result_buffer1          <= datapath_result; -- real part from addition
                                                state           <= s13;                         -- OPERATION ADDITION FINISHED  ->> OK
                                        elsif (gl_n = "100") then
                                                selected_op <= add_sub;
                                                state           <= s13;
                                        else
                                                state           <= s13;
                                        end if;
                                when s13 =>
                                        if (gl_n = "011") then
                                                done            <= '1';
                                                state           <= s0;
                                                result          <= result_buffer1;
                                                result_buffer           <= datapath_result; -- imag result from addition
                                        elsif (gl_n = "100") then
                                                result_buffer1          <= datapath_result; -- real result from subtraction
                                                state           <= s14;                 -- OPERATION SUBTRACTION FINISHED  ->> OK
                                        else
                                                state           <= s14;
                                        end if;
                                when s14 =>
                                        if (gl_n = "100") then
                                                state           <= s0; -- subtraction finished
                                                result_buffer           <= datapath_result; -- imag result from subtraction
                                                result          <= result_buffer1;
                                                done            <= '1';
                                        else
                                                state           <= s15;
                                        end if;
                                when s15 =>
                                        state           <= s16;
                                when s16 =>
                                        state           <= s17;
                                when s17 =>
                                        state           <= s19;
                                        selected_op <= add_sub;
                                when s19 =>
                                        state           <= s20;
                                when s20 =>
                                        if (gl_n = "010") then
                                                result_buffer1  <= datapath_result; -- real part of multiplication ->> OK
                                        elsif (gl_n = "001") then
                                                datapath_dataa  <= datapath_result; -- AC+BD
                                        end if;
                                        state                   <= s21;
                                when s21 =>
                                        state           <= s22;
                                when s22 =>
                                        if (gl_n = "010") then
                                                state   <= s0;
                                                result <= result_buffer1;
                                                result_buffer   <= datapath_result;
                                                done <= '1';
                                        else
                                                result_buffer <= datapath_result;
                                                state           <= s23; -- AD-BC
                                        end if;
                                when s23 =>
                                        state           <= s24;
                                        result                  <= datapath_result; -- for testing      
                                when s24 =>
                                        datapath_datab  <= datapath_result;     --CC+DD
                                        state           <= s25;
                                when s25 =>
                                        state           <= s26;
                                        selected_op <= div;
                                when s26 =>
                                        datapath_dataa  <= (result_buffer xor "10000000000000000000000000000000"); --AD-BC
                                        state           <= s27;
                                when s27 =>
                                        state           <= s28;
                                when s28 =>
                                        state           <= s29;
                                when s29 =>
                                        state           <= s30;
                                when s30 =>
                                        state           <= s31;
                                        result_buffer1          <= datapath_result;
                                when s31 =>
                                        state           <= s32;
                                when s32 =>
                                        state           <= s0;
                                        result_buffer           <= datapath_result;
                                        result          <= result_buffer1;
                                        done            <= '1';
                        end case;
                end if;
        end process state_machine;
 
end core;

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[/] [complexise/] [trunk/] [CI_complex_core.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	iloveliora	`-- -------------------------------------------------------`
2			`-- CI_complex_core`
3			`--`
4			`-- Purpose of this unit:`
5			`-- Speed up operations such as`
6			`-- - image processing`
7			`-- - .. to be completed`
8			`-- - .. to be completed`
9			`-- For examples see: no address available`
10			`-- Description:`
11			`--`
12			`--`
13			`-- Dependencies:`
14			`-- Version: not finished`
15			`-- Date: 24/5/2010`
16			`-- Created by Philipp Digeser`
17			`-- -------------------------------------------------------`
18			`-- The following pipe line settings are chosen for the mega functions`
19			`-- Multiplier 6`
20			`-- Adder 12`
21			`-- Divider 18*`
22			`-- -------------------------------------------------------`
23			`-- *The divider uses 6 pipe line stage, but since it has a`
24			`-- frequency of just clk/3 it is three times slower.`
25			`-- Additionally the pipeline can just be fed each third clock`
26			`-- this compromise was done to keep a high operation speed`
27			`-- of more than 300 MHz (STRATIX I), current cores are supposed`
28			`-- to be faster`
29			`-- -------------------------------------------------------`
30
31			`-- necessary libraries`
32			`library ieee;`
33			`use ieee.std_logic_1164.all;`
34			`use ieee.numeric_std.all;`
35
36			`ENTITY CI_complex_core IS`
37			`PORT(`
38			`----- general control signals ----------------------------`
39			`signal clk : in std_logic; -- CPU's master-input clk <required for multi-cycle>`
40			`signal reset : in std_logic; -- CPU's master asynchronous reset <required for multi-cycle>`
41			`signal clk_en: in std_logic; -- Clock-qualifier <required for multi-cycle>`
42			`signal start: in std_logic; -- True when this instr. issues <required for multi-cycle>`
43			`signal done: out std_logic; -- True when instr. completes <required for variable muli-cycle>`
44
45			`------ input signals from general purpose registers ------`
46			`signal dataa: in std_logic_vector (31 downto 0); -- operand A <always required>`
47			`signal datab: in std_logic_vector (31 downto 0); -- operand B <optional>`
48			`signal result : out std_logic_vector (31 downto 0); -- result <always required>`
49
50			`------ for choosing multiple instructions ----------------`
51			`signal n: in std_logic_vector (2 downto 0)); -- N-field selector <required for extended>`
52
53			`END CI_complex_core;`
54
55			`ARCHITECTURE core OF CI_complex_core IS`
56
57			`-- for state machine`
58			`type state_type is (s0, s1, s2, s3, s4, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, s32);`
59			`signal state : state_type;`
60
61			`type clock_type is (clk0, clk1, clk2);`
62			`signal clk_div1 : clock_type;`
63
64			`signal data_A: std_logic_vector(31 downto 0);`
65			`signal data_B: std_logic_vector(31 downto 0);`
66			`signal data_C: std_logic_vector(31 downto 0);`
67			`signal data_D: std_logic_vector(31 downto 0);`
68			`signal result_s0: std_logic_vector(31 downto 0);`
69
70			`signal datapath_dataa: std_logic_vector(31 downto 0);`
71			`signal datapath_datab: std_logic_vector(31 downto 0);`
72			`signal datapath_result: std_logic_vector(31 downto 0);`
73			`signal selected_op: std_logic_vector(1 downto 0);`
74			`signal result_buffer: std_logic_vector(31 downto 0);`
75			`signal result_buffer1: std_logic_vector(31 downto 0);`
76
77			`constant mult : std_logic_vector := "00";`
78			`constant add_sub : std_logic_vector := "01";`
79			`constant div : std_logic_vector := "10";`
80
81			`signal gl_nan: std_logic;`
82			`signal gl_overflow: std_logic;`
83			`signal gl_underflow: std_logic;`
84			`signal gl_zero: std_logic;`
85			`signal gl_div_by_zero: std_logic;`
86			`signal gl_n: std_logic_vector(2 downto 0); -- stores the value of n in the first state`
87
88			`---------- components -----------------------------------------`
89
90			`component datapath is`
91			`port`
92			`(`
93			`clk : IN STD_LOGIC;`
94			`clk_en : IN STD_LOGIC;`
95			`aclr : IN STD_LOGIC;`
96			`dataa : IN STD_LOGIC_VECTOR(31 DOWNTO 0);`
97			`datab : IN STD_LOGIC_VECTOR(31 DOWNTO 0);`
98			`sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);`
99			`NaN : OUT STD_LOGIC;`
100			`underflow : OUT STD_LOGIC;`
101			`zero : OUT STD_LOGIC;`
102			`overflow : OUT STD_LOGIC;`
103			`division_by_zero : OUT STD_LOGIC;`
104			`result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)`
105			`);`
106			`end component;`
107
108			`begin`
109
110
111			`datapath_inst : datapath PORT MAP(`
112
113			`clk => clk,`
114			`clk_en =>clk_en,`
115			`aclr =>reset,`
116			`dataa =>datapath_dataa,`
117			`datab =>datapath_datab,`
118			`sel =>selected_op,`
119			`NaN =>gl_nan,`
120			`underflow =>gl_underflow,`
121			`zero =>gl_zero,`
122			`overflow =>gl_overflow,`
123			`division_by_zero =>gl_div_by_zero,`
124			`result =>datapath_result`
125			`);`
126
127			`------ state machine ----------------------------------------------------`
128
129			`state_machine: process(clk, reset, clk_en) is`
130			`begin`
131			`if (reset='1') then`
132			`state <= s0;`
133			`elsif (falling_edge(clk) and clk_en = '1') then`
134			`-- list of modes (n):`
135			`-- 0: return / get A/C n = "000" -> ok`
136			`-- 1: division n = "001" -> ok`
137			`-- 2: multiplication n = "010" -> ok`
138			`-- 3: addition n = "011"`
139			`-- 4: subtraction n = "100"`
140			`-- 5: inverse n = "101"`
141			`-- 6: modulo n = "110"`
142			`-- 7: return errors n = "111" -> ok`
143			`case state is`
144			`when s0 =>`
145			`gl_n <= n; -- store n for further processes`
146			`if (start = '1') then`
147			`if (n = "000") then -- n=0 (load & return)`
148			`datapath_dataa <= dataa; -- load the first data`
149			`datapath_datab <= datab; -- load the second data`
150			`data_A <= dataa; -- and store both data`
151			`data_C <= datab;`
152			`result <= result_buffer; -- return one result`
153			`state <= s0; -- resetstate machine`
154			`done <= '1'; -- enable done`
155			`elsif (n<"111") then`
156			`if (n = "100") then -- like a subtraction`
157			`datapath_dataa <= data_A;`
158			`datapath_datab <= (data_C xor "10000000000000000000000000000000");`
159			`else`
160			`datapath_dataa <= dataa;`
161			`datapath_datab <= datab;`
162			`end if;`
163			`data_B <= dataa;`
164			`data_D <= datab;`
165			`done <= '0';`
166			`state <= s1;`
167			`elsif (n = "111") then -- RETURN THE ERRORS (Bit 31..27 of result)`
168			`state <= s0;`
169			`done <= '1';`
170			`result <= (gl_nan, gl_overflow, gl_underflow, gl_zero, gl_div_by_zero, others => '0');`
171			`else -- this state does not exist`
172			`state <= s0;`
173			`done <= '1';`
174			`end if;`
175			`end if;`
176			`when s1 =>`
177			`state <= s2;`
178			`if (gl_n = "100") then`
179			`datapath_dataa <= data_B; -- sub`
180			`datapath_datab <= (data_D xor "10000000000000000000000000000000");`
181			`else`
182			`datapath_dataa <= data_B; -- mult`
183			`datapath_datab <= data_C;`
184			`end if;`
185			`when s2 =>`
186			`state <= s3;`
187			`datapath_dataa <= data_A; --mult`
188			`datapath_datab <= data_D;`
189			`when s3 =>`
190			`state <= s4;`
191			`datapath_dataa <= data_C; --mult`
192			`datapath_datab <= data_C;`
193			`when s4 =>`
194			`state <= s6;`
195			`datapath_dataa <= data_D; --mult`
196			`datapath_datab <= data_D;`
197			`selected_op <= mult;`
198			`when s6 =>`
199			`state <= s7;`
200			`datapath_dataa <= datapath_result; -- AC addition`
201			`when s7 =>`
202			`state <= s8;`
203			`if (gl_n = "001") then`
204			`datapath_datab <= datapath_result; -- BD addition -- first addition starts`
205			`elsif (gl_n = "010") then`
206			`datapath_datab <= (datapath_result xor "10000000000000000000000000000000");`
207			`end if;`
208			`when s8 =>`
209			`state <= s9;`
210			`if (gl_n = "001") then`
211			`datapath_dataa <= (datapath_result xor "10000000000000000000000000000000"); -- -BC`
212			`elsif (gl_n = "010") then`
213			`datapath_dataa <= datapath_result; -- for multiplication we just need BC`
214			`end if;`
215			`when s9 =>`
216			`state <= s10;`
217			`datapath_datab <= datapath_result; -- AD`
218			`when s10 =>`
219			`state <= s11;`
220			`if (gl_n = "001") then --add`
221			`datapath_dataa <= datapath_result; -- CC`
222			`end if;`
223			`when s11 =>`
224			`if (gl_n = "001") then --add`
225			`datapath_datab <= datapath_result; -- DD`
226			`end if;`
227			`if (gl_n = "011") then`
228			`selected_op <= add_sub;`
229			`end if;`
230			`state <= s12;`
231			`when s12 =>`
232			`if (gl_n = "011") then`
233			`result_buffer1 <= datapath_result; -- real part from addition`
234			`state <= s13; -- OPERATION ADDITION FINISHED ->> OK`
235			`elsif (gl_n = "100") then`
236			`selected_op <= add_sub;`
237			`state <= s13;`
238			`else`
239			`state <= s13;`
240			`end if;`
241			`when s13 =>`
242			`if (gl_n = "011") then`
243			`done <= '1';`
244			`state <= s0;`
245			`result <= result_buffer1;`
246			`result_buffer <= datapath_result; -- imag result from addition`
247			`elsif (gl_n = "100") then`
248			`result_buffer1 <= datapath_result; -- real result from subtraction`
249			`state <= s14; -- OPERATION SUBTRACTION FINISHED ->> OK`
250			`else`
251			`state <= s14;`
252			`end if;`
253			`when s14 =>`
254			`if (gl_n = "100") then`
255			`state <= s0; -- subtraction finished`
256			`result_buffer <= datapath_result; -- imag result from subtraction`
257			`result <= result_buffer1;`
258			`done <= '1';`
259			`else`
260			`state <= s15;`
261			`end if;`
262			`when s15 =>`
263			`state <= s16;`
264			`when s16 =>`
265			`state <= s17;`
266			`when s17 =>`
267			`state <= s19;`
268			`selected_op <= add_sub;`
269			`when s19 =>`
270			`state <= s20;`
271			`when s20 =>`
272			`if (gl_n = "010") then`
273			`result_buffer1 <= datapath_result; -- real part of multiplication ->> OK`
274			`elsif (gl_n = "001") then`
275			`datapath_dataa <= datapath_result; -- AC+BD`
276			`end if;`
277			`state <= s21;`
278			`when s21 =>`
279			`state <= s22;`
280			`when s22 =>`
281			`if (gl_n = "010") then`
282			`state <= s0;`
283			`result <= result_buffer1;`
284			`result_buffer <= datapath_result;`
285			`done <= '1';`
286			`else`
287			`result_buffer <= datapath_result;`
288			`state <= s23; -- AD-BC`
289			`end if;`
290			`when s23 =>`
291			`state <= s24;`
292			`result <= datapath_result; -- for testing`
293			`when s24 =>`
294			`datapath_datab <= datapath_result; --CC+DD`
295			`state <= s25;`
296			`when s25 =>`
297			`state <= s26;`
298			`selected_op <= div;`
299			`when s26 =>`
300			`datapath_dataa <= (result_buffer xor "10000000000000000000000000000000"); --AD-BC`
301			`state <= s27;`
302			`when s27 =>`
303			`state <= s28;`
304			`when s28 =>`
305			`state <= s29;`
306			`when s29 =>`
307			`state <= s30;`
308			`when s30 =>`
309			`state <= s31;`
310			`result_buffer1 <= datapath_result;`
311			`when s31 =>`
312			`state <= s32;`
313			`when s32 =>`
314			`state <= s0;`
315			`result_buffer <= datapath_result;`
316			`result <= result_buffer1;`
317			`done <= '1';`
318			`end case;`
319			`end if;`
320			`end process state_machine;`
321
322			`end core;`