OpenCores
URL https://opencores.org/ocsvn/complexise/complexise/trunk

Subversion Repositories complexise

[/] [complexise/] [trunk/] [lpm_mux1.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 iloveliora
-- megafunction wizard: %LPM_MUX%
2
-- GENERATION: STANDARD
3
-- VERSION: WM1.0
4
-- MODULE: lpm_mux 
5
 
6
-- ============================================================
7
-- File Name: lpm_mux1.vhd
8
-- Megafunction Name(s):
9
--                      lpm_mux
10
--
11
-- Simulation Library Files(s):
12
--                      lpm
13
-- ============================================================
14
-- ************************************************************
15
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
16
--
17
-- 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
18
-- ************************************************************
19
 
20
 
21
--Copyright (C) 1991-2009 Altera Corporation
22
--Your use of Altera Corporation's design tools, logic functions 
23
--and other software and tools, and its AMPP partner logic 
24
--functions, and any output files from any of the foregoing 
25
--(including device programming or simulation files), and any 
26
--associated documentation or information are expressly subject 
27
--to the terms and conditions of the Altera Program License 
28
--Subscription Agreement, Altera MegaCore Function License 
29
--Agreement, or other applicable license agreement, including, 
30
--without limitation, that your use is for the sole purpose of 
31
--programming logic devices manufactured by Altera and sold by 
32
--Altera or its authorized distributors.  Please refer to the 
33
--applicable agreement for further details.
34
 
35
 
36
LIBRARY ieee;
37
USE ieee.std_logic_1164.all;
38
 
39
LIBRARY lpm;
40
USE lpm.lpm_components.all;
41
 
42
ENTITY lpm_mux1 IS
43
        PORT
44
        (
45
                data0x          : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
46
                data1x          : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
47
                data2x          : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
48
                sel             : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
49
                result          : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
50
        );
51
END lpm_mux1;
52
 
53
 
54
ARCHITECTURE SYN OF lpm_mux1 IS
55
 
56
--      type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
57
 
58
        SIGNAL sub_wire0        : STD_LOGIC_VECTOR (31 DOWNTO 0);
59
        SIGNAL sub_wire1        : STD_LOGIC_VECTOR (31 DOWNTO 0);
60
        SIGNAL sub_wire2        : STD_LOGIC_2D (2 DOWNTO 0, 31 DOWNTO 0);
61
        SIGNAL sub_wire3        : STD_LOGIC_VECTOR (31 DOWNTO 0);
62
        SIGNAL sub_wire4        : STD_LOGIC_VECTOR (31 DOWNTO 0);
63
 
64
BEGIN
65
        sub_wire4    <= data0x(31 DOWNTO 0);
66
        sub_wire3    <= data1x(31 DOWNTO 0);
67
        result    <= sub_wire0(31 DOWNTO 0);
68
        sub_wire1    <= data2x(31 DOWNTO 0);
69
        sub_wire2(2, 0)    <= sub_wire1(0);
70
        sub_wire2(2, 1)    <= sub_wire1(1);
71
        sub_wire2(2, 2)    <= sub_wire1(2);
72
        sub_wire2(2, 3)    <= sub_wire1(3);
73
        sub_wire2(2, 4)    <= sub_wire1(4);
74
        sub_wire2(2, 5)    <= sub_wire1(5);
75
        sub_wire2(2, 6)    <= sub_wire1(6);
76
        sub_wire2(2, 7)    <= sub_wire1(7);
77
        sub_wire2(2, 8)    <= sub_wire1(8);
78
        sub_wire2(2, 9)    <= sub_wire1(9);
79
        sub_wire2(2, 10)    <= sub_wire1(10);
80
        sub_wire2(2, 11)    <= sub_wire1(11);
81
        sub_wire2(2, 12)    <= sub_wire1(12);
82
        sub_wire2(2, 13)    <= sub_wire1(13);
83
        sub_wire2(2, 14)    <= sub_wire1(14);
84
        sub_wire2(2, 15)    <= sub_wire1(15);
85
        sub_wire2(2, 16)    <= sub_wire1(16);
86
        sub_wire2(2, 17)    <= sub_wire1(17);
87
        sub_wire2(2, 18)    <= sub_wire1(18);
88
        sub_wire2(2, 19)    <= sub_wire1(19);
89
        sub_wire2(2, 20)    <= sub_wire1(20);
90
        sub_wire2(2, 21)    <= sub_wire1(21);
91
        sub_wire2(2, 22)    <= sub_wire1(22);
92
        sub_wire2(2, 23)    <= sub_wire1(23);
93
        sub_wire2(2, 24)    <= sub_wire1(24);
94
        sub_wire2(2, 25)    <= sub_wire1(25);
95
        sub_wire2(2, 26)    <= sub_wire1(26);
96
        sub_wire2(2, 27)    <= sub_wire1(27);
97
        sub_wire2(2, 28)    <= sub_wire1(28);
98
        sub_wire2(2, 29)    <= sub_wire1(29);
99
        sub_wire2(2, 30)    <= sub_wire1(30);
100
        sub_wire2(2, 31)    <= sub_wire1(31);
101
        sub_wire2(1, 0)    <= sub_wire3(0);
102
        sub_wire2(1, 1)    <= sub_wire3(1);
103
        sub_wire2(1, 2)    <= sub_wire3(2);
104
        sub_wire2(1, 3)    <= sub_wire3(3);
105
        sub_wire2(1, 4)    <= sub_wire3(4);
106
        sub_wire2(1, 5)    <= sub_wire3(5);
107
        sub_wire2(1, 6)    <= sub_wire3(6);
108
        sub_wire2(1, 7)    <= sub_wire3(7);
109
        sub_wire2(1, 8)    <= sub_wire3(8);
110
        sub_wire2(1, 9)    <= sub_wire3(9);
111
        sub_wire2(1, 10)    <= sub_wire3(10);
112
        sub_wire2(1, 11)    <= sub_wire3(11);
113
        sub_wire2(1, 12)    <= sub_wire3(12);
114
        sub_wire2(1, 13)    <= sub_wire3(13);
115
        sub_wire2(1, 14)    <= sub_wire3(14);
116
        sub_wire2(1, 15)    <= sub_wire3(15);
117
        sub_wire2(1, 16)    <= sub_wire3(16);
118
        sub_wire2(1, 17)    <= sub_wire3(17);
119
        sub_wire2(1, 18)    <= sub_wire3(18);
120
        sub_wire2(1, 19)    <= sub_wire3(19);
121
        sub_wire2(1, 20)    <= sub_wire3(20);
122
        sub_wire2(1, 21)    <= sub_wire3(21);
123
        sub_wire2(1, 22)    <= sub_wire3(22);
124
        sub_wire2(1, 23)    <= sub_wire3(23);
125
        sub_wire2(1, 24)    <= sub_wire3(24);
126
        sub_wire2(1, 25)    <= sub_wire3(25);
127
        sub_wire2(1, 26)    <= sub_wire3(26);
128
        sub_wire2(1, 27)    <= sub_wire3(27);
129
        sub_wire2(1, 28)    <= sub_wire3(28);
130
        sub_wire2(1, 29)    <= sub_wire3(29);
131
        sub_wire2(1, 30)    <= sub_wire3(30);
132
        sub_wire2(1, 31)    <= sub_wire3(31);
133
        sub_wire2(0, 0)    <= sub_wire4(0);
134
        sub_wire2(0, 1)    <= sub_wire4(1);
135
        sub_wire2(0, 2)    <= sub_wire4(2);
136
        sub_wire2(0, 3)    <= sub_wire4(3);
137
        sub_wire2(0, 4)    <= sub_wire4(4);
138
        sub_wire2(0, 5)    <= sub_wire4(5);
139
        sub_wire2(0, 6)    <= sub_wire4(6);
140
        sub_wire2(0, 7)    <= sub_wire4(7);
141
        sub_wire2(0, 8)    <= sub_wire4(8);
142
        sub_wire2(0, 9)    <= sub_wire4(9);
143
        sub_wire2(0, 10)    <= sub_wire4(10);
144
        sub_wire2(0, 11)    <= sub_wire4(11);
145
        sub_wire2(0, 12)    <= sub_wire4(12);
146
        sub_wire2(0, 13)    <= sub_wire4(13);
147
        sub_wire2(0, 14)    <= sub_wire4(14);
148
        sub_wire2(0, 15)    <= sub_wire4(15);
149
        sub_wire2(0, 16)    <= sub_wire4(16);
150
        sub_wire2(0, 17)    <= sub_wire4(17);
151
        sub_wire2(0, 18)    <= sub_wire4(18);
152
        sub_wire2(0, 19)    <= sub_wire4(19);
153
        sub_wire2(0, 20)    <= sub_wire4(20);
154
        sub_wire2(0, 21)    <= sub_wire4(21);
155
        sub_wire2(0, 22)    <= sub_wire4(22);
156
        sub_wire2(0, 23)    <= sub_wire4(23);
157
        sub_wire2(0, 24)    <= sub_wire4(24);
158
        sub_wire2(0, 25)    <= sub_wire4(25);
159
        sub_wire2(0, 26)    <= sub_wire4(26);
160
        sub_wire2(0, 27)    <= sub_wire4(27);
161
        sub_wire2(0, 28)    <= sub_wire4(28);
162
        sub_wire2(0, 29)    <= sub_wire4(29);
163
        sub_wire2(0, 30)    <= sub_wire4(30);
164
        sub_wire2(0, 31)    <= sub_wire4(31);
165
 
166
        lpm_mux_component : lpm_mux
167
        GENERIC MAP (
168
                lpm_size => 3,
169
                lpm_type => "LPM_MUX",
170
                lpm_width => 32,
171
                lpm_widths => 2
172
        )
173
        PORT MAP (
174
                sel => sel,
175
                data => sub_wire2,
176
                result => sub_wire0
177
        );
178
 
179
 
180
 
181
END SYN;
182
 
183
-- ============================================================
184
-- CNX file retrieval info
185
-- ============================================================
186
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
187
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
188
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "3"
189
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
190
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
191
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
192
-- Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL data0x[31..0]
193
-- Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL data1x[31..0]
194
-- Retrieval info: USED_PORT: data2x 0 0 32 0 INPUT NODEFVAL data2x[31..0]
195
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
196
-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0]
197
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
198
-- Retrieval info: CONNECT: @data 1 2 32 0 data2x 0 0 32 0
199
-- Retrieval info: CONNECT: @data 1 1 32 0 data1x 0 0 32 0
200
-- Retrieval info: CONNECT: @data 1 0 32 0 data0x 0 0 32 0
201
-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
202
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
203
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE
204
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc FALSE
205
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE
206
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf FALSE
207
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE
208
-- Retrieval info: LIB_FILE: lpm

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.