OpenCores
URL https://opencores.org/ocsvn/const_encoder/const_encoder/trunk

Subversion Repositories const_encoder

[/] [const_encoder/] [web_uploads/] [const_enc.vhd] - Blame information for rev 6

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 root 
-- File: cost_enc.vhd
2 
-- Date:  Thursday, Nov 29 2001
3 
--
4 
-- www.opencores.org
5 
-- VHDL model of Constellation Encoder
6 
-- Purpose: VHDL RTL design containing a synthesizable Constellation
7 
-- encoder module for ADSL
8 
--
9 
-- Author: Sushanta Jyoti Sarmah (sushanta@@opencores.org )
10 
-- To Do: xxxx
11 
-----------------------------------------------------------------------
12 
 
13 
library ieee;
14 
 use ieee.std_logic_1164.all;
15 
 use ieee.std_logic_unsigned.all;
16 
 
17 
 
18 
entity cost_enc is
19 
        port (
20 
                clk:in std_logic;
21 
                msg_in: in std_logic;
22 
                b_in: in std_logic_vector (3 downto 0);
23 
                err:out std_logic;
24 
                x_out: out std_logic_vector (8 downto 0);
25 
                y_out: out std_logic_vector (8 downto 0));
26 
        end cost_enc;
27 
 
28 
architecture rtl of cost_enc is
29 
 
30 
function bin_int(a:std_logic_vector)return integer is
31 
---------------------------------------------------------------
32 
           variable a2,a1,x,y,i,j:integer;
33 
           begin
34 
              a1:=2;
35 
              a2:=0;
36 
              for i in 0 to 3 loop
37 
              if(a(i)='1')then a2:=a2+(a1 ** i);
38 
              end if;
39 
              end loop;
40 
              return(a2);
41 
           end bin_int;
42 
procedure k_map (k_in: in std_logic_vector(4 downto 0); signal kx_out,ky_out: out std_logic_vector(1 downto 0)) is
43 
 
44 
begin
45 
case k_in is
46 
 
47 
        when "00000" =>kx_out <= "00"; ky_out<="00";
48 
        when "00001" =>kx_out <= "00"; ky_out<="00";
49 
        when "00010" =>kx_out <= "00"; ky_out<="00";
50 
        when "00011" =>kx_out <= "00"; ky_out<="00";
51 
 
52 
        when "00100" =>kx_out <= "00"; ky_out<="11";
53 
        when "00101" =>kx_out <= "00"; ky_out<="11";
54 
        when "00110" =>kx_out <= "00"; ky_out<="11";
55 
        when "00111" =>kx_out <= "00"; ky_out<="11";
56 
 
57 
        when "01000" =>kx_out <= "11"; ky_out<="00";
58 
        when "01001" =>kx_out <= "11"; ky_out<="00";
59 
        when "01010" =>kx_out <= "11"; ky_out<="00";
60 
        when "01011" =>kx_out <= "11"; ky_out<="00";
61 
 
62 
        when "01100" =>kx_out <= "11"; ky_out<="11";
63 
        when "01101" =>kx_out <= "11"; ky_out<="11";
64 
        when "01110" =>kx_out <= "11"; ky_out<="11";
65 
        when "01111" =>kx_out <= "11"; ky_out<="11";
66 
 
67 
        when "10000" =>kx_out <= "01"; ky_out<="00";
68 
        when "10001" =>kx_out <= "01"; ky_out<="00";
69 
        when "10010" =>kx_out <= "00"; ky_out<="00";
70 
        when "10011" =>kx_out <= "10"; ky_out<="00";
71 
 
72 
        when "10100" =>kx_out <= "00"; ky_out<="01";
73 
        when "10101" =>kx_out <= "00"; ky_out<="01";
74 
        when "10110" =>kx_out <= "00"; ky_out<="10";
75 
        when "10111" =>kx_out <= "00"; ky_out<="01";
76 
 
77 
        when "11000" =>kx_out <= "11"; ky_out<="01";
78 
        when "11001" =>kx_out <= "11"; ky_out<="10";
79 
        when "11010" =>kx_out <= "11"; ky_out<="01";
80 
        when "11011" =>kx_out <= "11"; ky_out<="10";
81 
 
82 
        when "11100" =>kx_out <= "01"; ky_out<="11";
83 
        when "11101" =>kx_out <= "01"; ky_out<="11";
84 
        when "11110" =>kx_out <= "10"; ky_out<="11";
85 
        when "11111" =>kx_out <= "10"; ky_out<="11";
86 
        when others => null;
87 
 
88 
        end case;
89 
 
90 
end;
91 
 
92 
--signal tmp: std_logic_vector(4 downto 0);
93 
signal x_tmp,y_tmp: std_logic_vector(1 downto 0);
94 
-- signal s_in :std_logic_vector(4 downto 0):="10111";
95 
BEGIN
96 
 
97 
process(clk,b_in)
98 
 
99 
variable b :integer:=0;
100 
variable I :integer:=0;
101 
variable DATA : std_logic_vector( 15 downto 0):="0000000000000000";
102 
variable tmp: std_logic_vector(4 downto 0);
103 
--variable x_tmp,y_tmp: std_logic_vector(1 downto 0);
104 
variable tmp_b: std_logic_vector(2 downto 0);
105 
begin
106 
 
107 
                b:= bin_int(b_in);
108 
                if (clk'event and clk = '1') then
109 
                if (I< b) then
110 
           data(I):= msg_in;
111 
                I:= I+1;
112 
                else
113 
                I:=0;
114 
                err<= '0';
115 
                if ( b=1) then --special error case
116 
                err<='1';
117 
                end if;
118 
                if (b=2) then
119 
                x_out<= data(0)& data(0)& data(0)& data(0) & data(0)& data(0)& data(0)& data(0)& '1';
120 
                y_out<= data(1)& data(1)& data(1)& data(1) & data(1)& data(1)& data(1)& data(1)& '1';
121 
                end if;
122 
 
123 
                if (b=3) then
124 
                tmp_b:=data(2 downto 0);
125 
                case tmp_b is
126 
                when "000" =>x_out <= "000000001"; y_out<="000000011";
127 
                when "001" =>x_out <= "000000001"; y_out<="111111111";
128 
                when "010" =>x_out <= "111111111"; y_out<="000000001";
129 
                when "011" =>x_out <= "111111111"; y_out<="111111111";
130 
 
131 
                when "100" =>x_out <= "111111101"; y_out<="000000001";
132 
                when "101" =>x_out <= "000000001"; y_out<="000000011";
133 
                when "110" =>x_out <= "111111111"; y_out<="111111101";
134 
                when "111" =>x_out <= "000000011"; y_out<="111111111";
135 
 
136 
 
137 
                when others => null;
138 
 
139 
                end case;
140 
                end if;
141 
 
142 
 
143 
                if (b=4) then
144 
                x_out<= data(2)& data(2)& data(2)& data(2) & data(2)& data(2)& data(2)& data(0)& '1';
145 
                y_out<= data(3)& data(3)& data(3)& data(3) & data(3)& data(3)& data(3)& data(1)& '1';
146 
                end if;
147 
 
148 
                if (b=5) then
149 
                tmp:= data(4 downto 0);
150 
                k_map(tmp,x_tmp,y_tmp);
151 
                x_out<=x_tmp(1)& x_tmp(1)& x_tmp(1)& x_tmp(1) & x_tmp(1)& x_tmp(1)& x_tmp(0)& data(0)& '1';
152 
                y_out<= y_tmp(1)& y_tmp(1)& y_tmp(1)& y_tmp(1) & y_tmp(1)& y_tmp(1)& y_tmp(0)& data(1)& '1';
153 
                end if;
154 
 
155 
                if (b=6) then
156 
                x_out<= data(4)& data(4)& data(4)& data(4) & data(4)& data(4)& data(2)& data(0)& '1';
157 
                y_out<= data(5)& data(5)& data(5)& data(5) & data(5)& data(5)& data(3)& data(1)& '1';
158 
                end if;
159 
 
160 
                if (b=7) then
161 
                tmp:= data(6 downto 2);
162 
                k_map(tmp,x_tmp,y_tmp);
163 
                x_out<=x_tmp(1)& x_tmp(1)& x_tmp(1)& x_tmp(1) & x_tmp(1)& x_tmp(0)& data(2)& data(0)& '1';
164 
                y_out<= y_tmp(1)& y_tmp(1)& y_tmp(1)& y_tmp(1) & y_tmp(1)& y_tmp(0)& data(3)& data(1)& '1';
165 
                end if;
166 
                if (b=8) then
167 
                x_out<= data(6)& data(6)& data(6)& data(6) & data(6)& data(4)& data(2)& data(0)& '1';
168 
                y_out<= data(7)& data(7)& data(7)& data(7) & data(7)& data(5)& data(3)& data(1)& '1';
169 
                end if;
170 
                if (b=9) then
171 
                tmp:= data(7 downto 3);
172 
                k_map(tmp,x_tmp,y_tmp);
173 
                x_out<=x_tmp(1)& x_tmp(1)& x_tmp(1)& x_tmp(1) & x_tmp(0)& data(4)& data(2)& data(0)& '1';
174 
                y_out<= y_tmp(1)& y_tmp(1)& y_tmp(1)& y_tmp(1) & y_tmp(0)& data(5)& data(3)& data(1)& '1';
175 
                end if;
176 
                if (b=10) then
177 
                x_out<= data(8)& data(8)& data(8)& data(8) & data(6)& data(4)& data(2)& data(0)& '1';
178 
                y_out<= data(9)& data(9)& data(9)& data(9) & data(7)& data(5)& data(3)& data(1)& '1';
179 
                end if;
180 
                if (b=11) then
181 
                tmp:= data(8 downto 4);
182 
                k_map(tmp,x_tmp,y_tmp);
183 
                x_out<=x_tmp(1)& x_tmp(1)& x_tmp(1)& x_tmp(0) &data(6)& data(4)& data(2)& data(0)& '1';
184 
                y_out<= y_tmp(1)& y_tmp(1)& y_tmp(1)& y_tmp(0) & data(7)&data(5)& data(3)& data(1)& '1';
185 
                end if;
186 
                if (b=12) then
187 
                x_out<= data(10)& data(10)& data(10)& data(8) & data(6)& data(4)& data(2)& data(0)& '1';
188 
                y_out<= data(11)& data(11)& data(11)& data(9) & data(7)& data(5)& data(3)& data(1)& '1';
189 
                end if;
190 
                if (b=13) then
191 
                tmp:= data(9 downto 5);
192 
                k_map(tmp,x_tmp,y_tmp);
193 
                x_out<=x_tmp(1)& x_tmp(1)& x_tmp(1)& x_tmp(0) & data(6)& data(4)& data(2)& data(0)& '1';
194 
                y_out<= y_tmp(1)& y_tmp(1)& y_tmp(1)& y_tmp(0) & data(7)& data(5)& data(3)& data(1)& '1';
195 
                end if;
196 
                if (b=14) then
197 
                x_out<= data(12)& data(12)& data(10)& data(8) & data(6)& data(4)& data(2)& data(0)& '1';
198 
                y_out<= data(13)& data(13)& data(11)& data(9) & data(7)& data(5)& data(3)& data(1)& '1';
199 
                end if;
200 
                if ( b=15) then --special error case
201 
                err<='1';
202 
                end if;
203 
 
204 
 
205 
        end if;
206 
 end if;
207 
 
208 
 
209 
end process;
210 
 
211 
end RTL;
212 
 
213 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.