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1 5 N.Boukadid 
\section{Core1990}
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Core1990 is a point-to-point communication protocol using the royalty-free Interlaken protocol as it's foundation. It is designed by engineers and students of the Electronics Department of Nikhef (Amsterdam, The Netherlands) with large experiments at CERN (e.g. ATLAS) in mind. \\
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The development of Core1990 was intended to publish an open source protocol providing high throughput with a small percentage of overhead. Certain features like flow control and error detection are included.
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\begin{figure}[H]
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        \centering
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        \includegraphics[width=.6\textwidth]{Core1990_logo.jpg}
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        \caption{Core1990 logo}
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        \label{fig:Core1990_logo}
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\end{figure}
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\subsection{Features}
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Core1990 is packet with a lot of features providing data integrity and detection of errors while transmitting. These features are designed to be compliant with those featured in the interlaken protocol definition.
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\begin{itemize}
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        \item Lane rate transceiver dependent
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        \item Support framing consistent with the Interlaken Protocol Definition
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        \item Generates CRC-24 and CRC-32 for error checking
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        \item 58-bit independent synchronous scrambler
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        \item 64b/67b encoding
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        \item About 90\% bandwidth efficiency possible (depends on user configuration)
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        \item Self-synchronizing links
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        \item Flow control
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\end{itemize}
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\subsection{Obtaining and building Core 1990}
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Implementing the core in a design can be done easily by using the files provided with core1990.
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The complete process of obtaining and building Core1990 will be described including which files are required and should be included. The project has been designed in Xilinx Vivado 16.4 but should be compatible with other versions. The correct configuration of the ip cores will also be mentioned to ensure behavior as expected.
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The complete project can be downloaded through the download link on the OpenCores site itself or through SVN. For OpenCores the link is \href{https://opencores.org/project/core1990_interlaken}{https://opencores.org/project/core1990\\\_interlaken} and the SVN links is \href{https://opencores.org/ocsvn/core1990_interlaken/core1990_interlaken/trunk}{https://opencores.org/ocsvn/core1990\_interlaken/core1990\\\_interlaken/trunk} in case this is preferred.\\
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 \begin{forest}
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        pic dir tree,
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        where level=0{}{% folder icons by default; override using file for file icons
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                directory,
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        },
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        [Core1990
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                [constraints]
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                [scripts]
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                [simulation]
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                [sources
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                        [Interlaken\_Interface.vhd, file, label=right: \small{The main file}]
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                        [ip\_cores
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                                [clk\_40MHz.xci, file]
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                                [RX\_FIFO.xci, file]
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                                [Transceiver\_10g\_64b67b.xci, file]
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                                [TX\_FIFO.xci, file] ]
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                        [CRC
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                                [crc-24.vhd,file]
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                                [crc-32.vhd, file] ]
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                        [Receiver
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                                [interlaken\_receiver.vhd,file]
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                                [decoder.vhd, file]
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                                [deframing\_burst.vhd, file]
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                                [deframing\_meta.vhd, file]
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                                [descrambler.vhd, file] ]
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                        [Transmitter
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                                [interlaken\_transmitter.vhd,file]
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                                [encoder.vhd, file]
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                                [framing\_burst.vhd, file]
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                                [framing\_meta.vhd, file]
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                                [scrambler.vhd, file] ]
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                ]
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        ]
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 \end{forest}
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The directory tree depicts the file structure in the sources folder. This should contain several files to configure the ip cores, a folder containing two crc error detection modules, a receiver and transmitter folder containing the module files. A main file is included in the folder that is meant for the top level connecting all modules correctly to each other.
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Besides these files there are also three different folders. One contains the constraints which are responsible for connecting the physical pins to the signals in the package and providing clock information to the fitter of the design. Another folder contains several scripts to build the project by just running a single script. Another script will be able to generate testbenches on request of the user and a script generates the implementation of the design. The simulation folder contains a lot of testbenches used to simulate all the components included in the design.
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\begin{forest}
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        pic dir tree,
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        where level=0{}{% folder icons by default; override using file for file icons
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                directory,
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        },
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        [Core1990
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                [constraints
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                        [Core1990\_Constraints.xdc, file] ]
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                [scripts
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                        [implementation.tcl, file]
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                        [simulation.tcl, file]
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                        [vivado\_import\_virtex7.tcl, file]     ]
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                [simulation]
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                [sources]
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        ]
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\end{forest}
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For building the project Vivado has to be opened and the vivado\_import\_virtex7.tcl has to be executed. This can be done by changing the directory in the tcl console to the scripts folder and then giving the command 'source vivado\_import\_virtex7.tcl'. This will add the project folder to the directory tree and contains the just generated project.
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Simulation can be done with a separate script which can be run by the command 'source simulation.tcl'. After this a short explanation of the command this script accepts should appear. For example if the user would like to simulate the decoder, this can be done by giving the command 'simulate decoder' in the tcl console.
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\subsection{Transceiver IP Core}
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Configuring the transceiver right is essential for the functional behavior of the protocol. In case wrong configuration is used, no data or corrupted data will arrive at the receiving side. This section will guide the user to setting up the transceiver in an easy way without adjusting too many clocks, targeting the VC707 board.\\
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When configuring the core a separate window will pop up. The fist tab named GT Selection should already have the GTX as GT Type selected and the shared logic should be included in the core, not the example design.
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After this the second tab will provide more important options. The line rate should be set to 10 Gbps while the reference clock can be set at 125 MHz. This clock is available on the board at IO pins AH7 and AH8, REFCLK0\_Q0. Using the QPLL GTX X1Y2 can be used. Figure \ref{fig:IP_TransceiverConf1} shows the correct configuration.
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\begin{figure}[H]
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        \centering
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        \includegraphics[width=.8\textwidth]{IP_TransceiverConf1.png}
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        \caption{Transceiver lane rate and reference clock selection}
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        \label{fig:IP_TransceiverConf1}
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\end{figure}
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The encoding and clocking tab shows other important settings. For both the TX and RX, the external data width should be set at 64-bits while the internal data width is 32 bits. Encoding has to be set at 64B/67B with Internal Sequence Counter and decoding has to be set at 64B/67B. The DRP/System Clock Frequency has to be set at 40 MHz. Figure \ref{fig:IP_TransceiverConf2} shows the right settings.
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\begin{figure}[H]
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        \centering
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        \includegraphics[width=.8\textwidth]{IP_TransceiverConf2.png}
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        \caption{Transceiver encoding and system clock selection}
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        \label{fig:IP_TransceiverConf2}
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\end{figure}
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The other tabs are not important and no settings should be changed in these tabs. Figure \ref{fig:IP_TransceiverConf3} shows a complete summary of the features included with the transceiver when this core will be generate. The user should have the same settings on screen.
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\begin{figure}[H]
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        \centering
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        \includegraphics[width=.8\textwidth]{IP_TransceiverConf3.png}
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        \caption{Transceiver summary of configuration}
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        \label{fig:IP_TransceiverConf3}
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\end{figure}
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\newpage
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\subsection{System Clock IP Core}
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The system clock will be generated using a 200 MHz input at IO pins E18 and E19. The frequency will be scaled down using the Xilinx Clocking Wizard which generates an IP core.
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\begin{figure}[H]
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        \centering
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        \includegraphics[width=\textwidth]{IP_CLK40Conf1.png}
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        \caption{System clock setting the board interface}
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        \label{fig:IP_CLK40Conf1}
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\end{figure}
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\begin{figure}[H]
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        \centering
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        \includegraphics[width=\textwidth]{IP_CLK40Conf2.png}
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        \caption{System clock setting the options}
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        \label{fig:IP_CLK40Conf2}
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\end{figure}
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\begin{figure}[H]
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        \centering
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        \includegraphics[width=\textwidth]{IP_CLK40Conf3.png}
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        \caption{System clock configuring the output clock}
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        \label{fig:IP_CLK40Conf3}
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\end{figure}
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\begin{figure}[H]
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        \centering
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        \includegraphics[width=\textwidth]{IP_CLK40Conf4.png}
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        \caption{System clock summary of configuration}
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        \label{fig:IP_CLK40Conf4}
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\end{figure}
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\newpage
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\subsection{FIFO IP Cores}
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\subsection{Simulating the core}
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Simulation of the core1990 protocol can easily be configure by running the simulation script.
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\newpage
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Core 1990 explores state of the art point-to-point communication protocols.
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It proposes a simple and standard solution, which is as much as possible vendor independent, and based on the Open Source Interlaken protocol.
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\url{https://null.53bits.co.uk/index.php?page=encoding-schemes}

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