OpenCores
URL https://opencores.org/ocsvn/core1990_interlaken/core1990_interlaken/trunk

Subversion Repositories core1990_interlaken

[/] [core1990_interlaken/] [trunk/] [gateware/] [simulation/] [testbench_interlaken_interface_behav.wcfg] - Blame information for rev 6

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 N.Boukadid
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 
      Interface
25 
      label
26
27
28 
         System_Clock_In_P
29 
         System_Clock_In_P
30
31
32 
         System_Clock_In_N
33 
         System_Clock_In_N
34
35
36 
         GTREFCLK_IN_P
37 
         GTREFCLK_IN_P
38
39
40 
         GTREFCLK_IN_N
41 
         GTREFCLK_IN_N
42
43
44 
         System_Clock_Gen
45 
         System_Clock_Gen
46
47
48 
         TX_Data[63:0]
49 
         TX_Data[63:0]
50
51
52 
         RX_Data[63:0]
53 
         RX_Data[63:0]
54
55
56 
         TX_Out_P
57 
         TX_Out_P
58
59
60 
         TX_Out_N
61 
         TX_Out_N
62
63
64 
         RX_In_P
65 
         RX_In_P
66
67
68 
         RX_In_N
69 
         RX_In_N
70
71
72 
         TX_SOP
73 
         TX_SOP
74
75
76 
         TX_EOP
77 
         TX_EOP
78
79
80 
         TX_EOP_Valid[2:0]
81 
         TX_EOP_Valid[2:0]
82
83
84 
         TX_FlowControl[15:0]
85 
         TX_FlowControl[15:0]
86
87
88 
         TX_Channel[7:0]
89 
         TX_Channel[7:0]
90
91
92 
         RX_SOP
93 
         RX_SOP
94
95
96 
         RX_EOP
97 
         RX_EOP
98
99
100 
         RX_EOP_Valid[2:0]
101 
         RX_EOP_Valid[2:0]
102
103
104 
         RX_FlowControl[15:0]
105 
         RX_FlowControl[15:0]
106
107
108 
         RX_Channel[7:0]
109 
         RX_Channel[7:0]
110
111
112 
         TX_Link_Up
113 
         TX_Link_Up
114
115
116 
         RX_Link_Up
117 
         RX_Link_Up
118
119
120 
         TX_FIFO_Full
121 
         TX_FIFO_Full
122
123
124 
         TX_FIFO_Empty
125 
         TX_FIFO_Empty
126
127
128 
         RX_FIFO_Full
129 
         RX_FIFO_Full
130
131
132 
         RX_FIFO_Empty
133 
         RX_FIFO_Empty
134
135
136 
         Decoder_lock
137 
         Decoder_lock
138
139
140 
         Descrambler_lock
141 
         Descrambler_lock
142
143
144 
         CRC24_Error
145 
         CRC24_Error
146
147
148 
         CRC32_Error
149 
         CRC32_Error
150
151
152 
         System_Clock_40
153 
         System_Clock_40
154
155
156 
         TX_User_Clock
157 
         TX_User_Clock
158
159
160 
         RX_User_Clock
161 
         RX_User_Clock
162
163
164 
         Data_Transferred[66:0]
165 
         Data_Transferred[66:0]
166
167
168 
         RX_prog_full[15:0]
169 
         RX_prog_full[15:0]
170
171
172 
         FlowControl[15:0]
173 
         FlowControl[15:0]
174
175
176 
         RX_Datavalid_Out
177 
         RX_Datavalid_Out
178
179
180 
         RX_Header_Out[2:0]
181 
         RX_Header_Out[2:0]
182
183
184 
         RX_Headervalid_Out
185 
         RX_Headervalid_Out
186
187
188 
         RX_Gearboxslip_In
189 
         RX_Gearboxslip_In
190
191
192 
         RX_Resetdone_Out
193 
         RX_Resetdone_Out
194
195
196 
         TX_Gearboxready_Out
197 
         TX_Gearboxready_Out
198
199
200 
         TX_Header_In[2:0]
201 
         TX_Header_In[2:0]
202
203
204 
         TX_Startseq_In
205 
         TX_Startseq_In
206
207
208 
         TX_Resetdone_Out
209 
         TX_Resetdone_Out
210
211
212 
         Data_Transceiver_In[63:0]
213 
         Data_Transceiver_In[63:0]
214
215
216 
         Data_Transceiver_Out[63:0]
217 
         Data_Transceiver_Out[63:0]
218
219
220 
         GT0_DATA_VALID_IN
221 
         GT0_DATA_VALID_IN
222
223
224 
         GT0_TX_FSM_RESET_DONE_OUT
225 
         GT0_TX_FSM_RESET_DONE_OUT
226
227
228 
         locked
229 
         locked
230
231
232 
         reset
233 
         reset
234
235
236 
         BurstMax
237 
         BurstMax
238
239
240 
         BurstShort
241 
         BurstShort
242
243
244 
         PacketLength
245 
         PacketLength
246
247
248
249 
      InterlakenTX
250 
      label
251
252
253 
         write_clk
254 
         write_clk
255
256
257 
         clk
258 
         clk
259
260
261 
         reset
262 
         reset
263
264
265 
         TX_Data_In[63:0]
266 
         TX_Data_In[63:0]
267
268
269 
         TX_Data_Out[66:0]
270 
         TX_Data_Out[66:0]
271
272
273 
         TX_Enable
274 
         TX_Enable
275
276
277 
         TX_SOP
278 
         TX_SOP
279
280
281 
         TX_EOP_Valid[2:0]
282 
         TX_EOP_Valid[2:0]
283
284
285 
         TX_EOP
286 
         TX_EOP
287
288
289 
         TX_Channel[7:0]
290 
         TX_Channel[7:0]
291
292
293 
         TX_Gearboxready
294 
         TX_Gearboxready
295
296
297 
         TX_Startseq
298 
         TX_Startseq
299
300
301 
         TX_FlowControl[15:0]
302 
         TX_FlowControl[15:0]
303
304
305 
         RX_prog_full[15:0]
306 
         RX_prog_full[15:0]
307
308
309 
         TX_Link_Up
310 
         TX_Link_Up
311
312
313 
         pres_state
314 
         pres_state
315
316
317 
         next_state
318 
         next_state
319
320
321 
         Data_Input[68:0]
322 
         Data_Input[68:0]
323
324
325 
         Data_FIFO_In[68:0]
326 
         Data_FIFO_In[68:0]
327 
         #00FF7F
328 
         true
329
330
331 
         FIFO_Full
332 
         FIFO_Full
333 
         #00FF7F
334 
         true
335
336
337 
         FIFO_Empty
338 
         FIFO_Empty
339 
         #00FF7F
340 
         true
341
342
343 
         FIFO_prog_full
344 
         FIFO_prog_full
345 
         #00FF7F
346 
         true
347
348
349 
         FIFO_prog_empty
350 
         FIFO_prog_empty
351 
         #00FF7F
352 
         true
353
354
355 
         FIFO_Read_Data
356 
         FIFO_Read_Data
357 
         #00FF7F
358 
         true
359
360
361 
         FIFO_Write_Data
362 
         FIFO_Write_Data
363 
         #00FF7F
364 
         true
365
366
367 
         FIFO_Read_Count[4:0]
368 
         FIFO_Read_Count[4:0]
369 
         #00FF7F
370 
         true
371
372
373 
         FIFO_Write_Count[4:0]
374 
         FIFO_Write_Count[4:0]
375 
         #00FF7F
376 
         true
377
378
379 
         Data_Burst_In[68:0]
380 
         Data_Burst_In[68:0]
381 
         #FF00FF
382 
         true
383
384
385 
         Data_Burst_Out[63:0]
386 
         Data_Burst_Out[63:0]
387 
         #FF00FF
388 
         true
389
390
391 
         Data_Valid_Burst_Out
392 
         Data_Valid_Burst_Out
393 
         #FF00FF
394 
         true
395
396
397 
         Data_Control_Burst_Out
398 
         Data_Control_Burst_Out
399 
         #FF00FF
400 
         true
401
402
403 
         Data_Meta_Out[63:0]
404 
         Data_Meta_Out[63:0]
405 
         #E0FFFF
406 
         true
407
408
409 
         Data_Control_Meta_Out
410 
         Data_Control_Meta_Out
411 
         #E0FFFF
412 
         true
413
414
415 
         Data_Valid_Meta_Out
416 
         Data_Valid_Meta_Out
417 
         #E0FFFF
418 
         true
419
420
421 
         FIFO_Read_Meta
422 
         FIFO_Read_Meta
423 
         #E0FFFF
424 
         true
425
426
427 
         Data_Control_Scrambler_Out
428 
         Data_Control_Scrambler_Out
429
430
431 
         Data_Valid_Scrambler_Out
432 
         Data_Valid_Scrambler_Out
433
434
435 
         Data_Scrambler_Out[63:0]
436 
         Data_Scrambler_Out[63:0]
437
438
439 
         HealthStatus[1:0]
440 
         HealthStatus[1:0]
441
442
443 
         Gearbox_Count
444 
         Gearbox_Count
445
446
447 
         Gearbox_Pause
448 
         Gearbox_Pause
449
450
451 
         GearboxSignal
452 
         GearboxSignal
453
454
455 
         BurstMax
456 
         BurstMax
457
458
459 
         BurstShort
460 
         BurstShort
461
462
463 
         PacketLength
464 
         PacketLength
465
466
467
468 
      Burstframing
469 
      label
470
471
472 
         clk
473 
         clk
474
475
476 
         reset
477 
         reset
478
479
480 
         TX_Enable
481 
         TX_Enable
482
483
484 
         TX_SOP
485 
         TX_SOP
486
487
488 
         TX_ValidBytes[2:0]
489 
         TX_ValidBytes[2:0]
490
491
492 
         TX_EOP
493 
         TX_EOP
494
495
496 
         TX_Channel[7:0]
497 
         TX_Channel[7:0]
498
499
500 
         Data_in[63:0]
501 
         Data_in[63:0]
502
503
504 
         Data_in_valid
505 
         Data_in_valid
506
507
508 
         Data_out[63:0]
509 
         Data_out[63:0]
510 
         #E0FFFF
511 
         true
512
513
514 
         Data_valid_out
515 
         Data_valid_out
516 
         #E0FFFF
517 
         true
518
519
520 
         Data_control_out
521 
         Data_control_out
522 
         #E0FFFF
523 
         true
524
525
526 
         TX_FlowControl[15:0]
527 
         TX_FlowControl[15:0]
528
529
530 
         RX_prog_full[15:0]
531 
         RX_prog_full[15:0]
532
533
534 
         FIFO_data[4:0]
535 
         FIFO_data[4:0]
536
537
538 
         FIFO_meta
539 
         FIFO_meta
540 
         #FFD700
541 
         true
542
543
544 
         FIFO_read
545 
         FIFO_read
546 
         #FFD700
547 
         true
548
549
550 
         Gearboxready
551 
         Gearboxready
552 
         #FFD700
553 
         true
554
555
556 
         FIFO_Empty
557 
         FIFO_Empty
558
559
560 
         FIFO_readreq
561 
         FIFO_readreq
562
563
564 
         pres_state
565 
         pres_state
566
567
568 
         next_state
569 
         next_state
570
571
572 
         Data_Temp[63:0]
573 
         Data_Temp[63:0]
574 
         #E0FFFF
575 
         true
576
577
578 
         Data_valid_temp
579 
         Data_valid_temp
580 
         #E0FFFF
581 
         true
582
583
584 
         valid_temp
585 
         valid_temp
586
587
588 
         Byte_Counter
589 
         Byte_Counter
590
591
592 
         Word_Control_out
593 
         Word_Control_out
594
595
596 
         Data_P1[63:0]
597 
         Data_P1[63:0]
598
599
600 
         Data_P2[63:0]
601 
         Data_P2[63:0]
602
603
604 
         ControlValid_P1[1:0]
605 
         ControlValid_P1[1:0]
606
607
608 
         ControlValid_P2[1:0]
609 
         ControlValid_P2[1:0]
610
611
612 
         CRC24_TX[63:0]
613 
         CRC24_TX[63:0]
614 
         #E0FFFF
615 
         true
616
617
618 
         Data_Valid
619 
         Data_Valid
620 
         #E0FFFF
621 
         true
622
623
624 
         Data_Control
625 
         Data_Control
626
627
628 
         CRC24_Out[31:0]
629 
         CRC24_Out[31:0]
630
631
632 
         CRC24_En
633 
         CRC24_En
634
635
636 
         CRC24_RST
637 
         CRC24_RST
638
639
640 
         CRC24_P1
641 
         CRC24_P1
642
643
644 
         CRC24_RST_P1
645 
         CRC24_RST_P1
646
647
648 
         CRC24_Stored[31:0]
649 
         CRC24_Stored[31:0]
650
651
652 
         CRC24_Ready
653 
         CRC24_Ready
654
655
656 
         CRC_P1
657 
         CRC_P1
658
659
660 
         CRC_P2
661 
         CRC_P2
662
663
664 
         Gearboxready_P1
665 
         Gearboxready_P1
666
667
668 
         CalcCrc
669 
         CalcCrc
670
671
672 
         BurstMax
673 
         BurstMax
674
675
676 
         BurstShort
677 
         BurstShort
678
679
680
681 
      Metaframing
682 
      label
683
684
685 
         clk
686 
         clk
687
688
689 
         reset
690 
         reset
691
692
693 
         TX_Enable
694 
         TX_Enable
695
696
697 
         HealthLane
698 
         HealthLane
699
700
701 
         HealthInterface
702 
         HealthInterface
703
704
705 
         Data_In[63:0]
706 
         Data_In[63:0]
707
708
709 
         Data_Out[63:0]
710 
         Data_Out[63:0]
711
712
713 
         Data_Valid_In
714 
         Data_Valid_In
715
716
717 
         Data_Valid_Out
718 
         Data_Valid_Out
719
720
721 
         Data_Control_In
722 
         Data_Control_In
723
724
725 
         Data_Control_Out
726 
         Data_Control_Out
727
728
729 
         Gearboxready
730 
         Gearboxready
731
732
733 
         FIFO_read
734 
         FIFO_read
735
736
737 
         pres_state
738 
         pres_state
739
740
741 
         next_state
742 
         next_state
743
744
745 
         Packet_Counter
746 
         Packet_Counter
747
748
749 
         Data_Control
750 
         Data_Control
751
752
753 
         Data_Control_Meta
754 
         Data_Control_Meta
755
756
757 
         Data_Control_Burst
758 
         Data_Control_Burst
759
760
761 
         Data_Valid
762 
         Data_Valid
763
764
765 
         Data_P1[63:0]
766 
         Data_P1[63:0]
767
768
769 
         Data_P2[63:0]
770 
         Data_P2[63:0]
771
772
773 
         Data_P3[63:0]
774 
         Data_P3[63:0]
775
776
777 
         Control_P1
778 
         Control_P1
779
780
781 
         Control_P2
782 
         Control_P2
783
784
785 
         Control_P3
786 
         Control_P3
787
788
789 
         Data_valid_p1
790 
         Data_valid_p1
791
792
793 
         Data_valid_p2
794 
         Data_valid_p2
795
796
797 
         Data_valid_p3
798 
         Data_valid_p3
799
800
801 
         Data_valid_framed
802 
         Data_valid_framed
803
804
805 
         Data_ControlValid_P1[1:0]
806 
         Data_ControlValid_P1[1:0]
807
808
809 
         Data_ControlValid_P2[1:0]
810 
         Data_ControlValid_P2[1:0]
811
812
813 
         Data_Framed[63:0]
814 
         Data_Framed[63:0]
815
816
817 
         Data_Framed_P1[63:0]
818 
         Data_Framed_P1[63:0]
819
820
821 
         Data_Framed_P2[63:0]
822 
         Data_Framed_P2[63:0]
823
824
825 
         CRC32_Out[31:0]
826 
         CRC32_Out[31:0]
827
828
829 
         CRC32_En
830 
         CRC32_En
831
832
833 
         CRC32_Rst
834 
         CRC32_Rst
835
836
837 
         CalcCRC
838 
         CalcCRC
839
840
841 
         CRC32_Ready
842 
         CRC32_Ready
843
844
845 
         Gearboxready_P1
846 
         Gearboxready_P1
847
848
849 
         CRC32_Rst_P1
850 
         CRC32_Rst_P1
851
852
853 
         PacketLength
854 
         PacketLength
855
856
857
858 
      Scrambler
859 
      label
860
861 
         Clk
862 
         Clk
863
864
865 
         Scram_Rst
866 
         Scram_Rst
867
868
869 
         Data_In[63:0]
870 
         Data_In[63:0]
871
872
873 
         Data_Out[63:0]
874 
         Data_Out[63:0]
875
876
877 
         Lane_Number[3:0]
878 
         Lane_Number[3:0]
879
880
881 
         Scrambler_En
882 
         Scrambler_En
883
884
885 
         Data_Control_In
886 
         Data_Control_In
887
888
889 
         Data_Control_Out
890 
         Data_Control_Out
891
892
893 
         Data_Valid_In
894 
         Data_Valid_In
895
896
897 
         Data_Valid_Out
898 
         Data_Valid_Out
899
900
901 
         Gearboxready
902 
         Gearboxready
903
904
905 
         Poly[57:0]
906 
         Poly[57:0]
907
908
909 
         Shiftreg[63:0]
910 
         Shiftreg[63:0]
911
912
913
914 
      Encoder
915 
      label
916
917 
         Clk
918 
         Clk
919
920
921 
         Data_In[63:0]
922 
         Data_In[63:0]
923
924
925 
         Data_Out[66:0]
926 
         Data_Out[66:0]
927
928
929 
         Data_Control
930 
         Data_Control
931
932
933 
         Data_valid_in
934 
         Data_valid_in
935
936
937 
         Data_valid_out
938 
         Data_valid_out
939
940
941 
         Encoder_En
942 
         Encoder_En
943
944
945 
         Encoder_Rst
946 
         Encoder_Rst
947
948
949 
         Offset[7:0]
950 
         Offset[7:0]
951
952
953 
         Gearboxready
954 
         Gearboxready
955
956
957
958 
      Transceiver
959 
      label
960
961 
         SOFT_RESET_TX_IN
962 
         SOFT_RESET_TX_IN
963
964
965 
         SOFT_RESET_RX_IN
966 
         SOFT_RESET_RX_IN
967
968
969 
         DONT_RESET_ON_DATA_ERROR_IN
970 
         DONT_RESET_ON_DATA_ERROR_IN
971
972
973 
         Q0_CLK0_GTREFCLK_PAD_N_IN
974 
         Q0_CLK0_GTREFCLK_PAD_N_IN
975
976
977 
         Q0_CLK0_GTREFCLK_PAD_P_IN
978 
         Q0_CLK0_GTREFCLK_PAD_P_IN
979
980
981 
         GT0_TX_FSM_RESET_DONE_OUT
982 
         GT0_TX_FSM_RESET_DONE_OUT
983
984
985 
         GT0_RX_FSM_RESET_DONE_OUT
986 
         GT0_RX_FSM_RESET_DONE_OUT
987
988
989 
         GT0_DATA_VALID_IN
990 
         GT0_DATA_VALID_IN
991
992
993 
         GT0_TX_MMCM_LOCK_OUT
994 
         GT0_TX_MMCM_LOCK_OUT
995
996
997 
         GT0_RX_MMCM_LOCK_OUT
998 
         GT0_RX_MMCM_LOCK_OUT
999
1000
1001 
         GT0_TXUSRCLK_OUT
1002 
         GT0_TXUSRCLK_OUT
1003
1004
1005 
         GT0_TXUSRCLK2_OUT
1006 
         GT0_TXUSRCLK2_OUT
1007
1008
1009 
         GT0_RXUSRCLK_OUT
1010 
         GT0_RXUSRCLK_OUT
1011
1012
1013 
         GT0_RXUSRCLK2_OUT
1014 
         GT0_RXUSRCLK2_OUT
1015
1016
1017 
         gt0_drpaddr_in[8:0]
1018 
         gt0_drpaddr_in[8:0]
1019
1020
1021 
         gt0_drpdi_in[15:0]
1022 
         gt0_drpdi_in[15:0]
1023
1024
1025 
         gt0_drpdo_out[15:0]
1026 
         gt0_drpdo_out[15:0]
1027
1028
1029 
         gt0_drpen_in
1030 
         gt0_drpen_in
1031
1032
1033 
         gt0_drprdy_out
1034 
         gt0_drprdy_out
1035
1036
1037 
         gt0_drpwe_in
1038 
         gt0_drpwe_in
1039
1040
1041 
         gt0_dmonitorout_out[7:0]
1042 
         gt0_dmonitorout_out[7:0]
1043
1044
1045 
         gt0_eyescanreset_in
1046 
         gt0_eyescanreset_in
1047
1048
1049 
         gt0_rxuserrdy_in
1050 
         gt0_rxuserrdy_in
1051
1052
1053 
         gt0_eyescandataerror_out
1054 
         gt0_eyescandataerror_out
1055
1056
1057 
         gt0_eyescantrigger_in
1058 
         gt0_eyescantrigger_in
1059
1060
1061 
         gt0_rxdata_out[63:0]
1062 
         gt0_rxdata_out[63:0]
1063
1064
1065 
         gt0_gtxrxp_in
1066 
         gt0_gtxrxp_in
1067
1068
1069 
         gt0_gtxrxn_in
1070 
         gt0_gtxrxn_in
1071
1072
1073 
         gt0_rxdfelpmreset_in
1074 
         gt0_rxdfelpmreset_in
1075
1076
1077 
         gt0_rxmonitorout_out[6:0]
1078 
         gt0_rxmonitorout_out[6:0]
1079
1080
1081 
         gt0_rxmonitorsel_in[1:0]
1082 
         gt0_rxmonitorsel_in[1:0]
1083
1084
1085 
         gt0_rxoutclkfabric_out
1086 
         gt0_rxoutclkfabric_out
1087
1088
1089 
         gt0_rxdatavalid_out
1090 
         gt0_rxdatavalid_out
1091
1092
1093 
         gt0_rxheader_out[2:0]
1094 
         gt0_rxheader_out[2:0]
1095
1096
1097 
         gt0_rxheadervalid_out
1098 
         gt0_rxheadervalid_out
1099
1100
1101 
         gt0_rxgearboxslip_in
1102 
         gt0_rxgearboxslip_in
1103
1104
1105 
         gt0_gtrxreset_in
1106 
         gt0_gtrxreset_in
1107
1108
1109 
         gt0_rxpmareset_in
1110 
         gt0_rxpmareset_in
1111
1112
1113 
         gt0_rxresetdone_out
1114 
         gt0_rxresetdone_out
1115
1116
1117 
         gt0_gttxreset_in
1118 
         gt0_gttxreset_in
1119
1120
1121 
         gt0_txuserrdy_in
1122 
         gt0_txuserrdy_in
1123
1124
1125 
         gt0_txdata_in[63:0]
1126 
         gt0_txdata_in[63:0]
1127
1128
1129 
         gt0_gtxtxn_out
1130 
         gt0_gtxtxn_out
1131
1132
1133 
         gt0_gtxtxp_out
1134 
         gt0_gtxtxp_out
1135
1136
1137 
         gt0_txoutclkfabric_out
1138 
         gt0_txoutclkfabric_out
1139
1140
1141 
         gt0_txoutclkpcs_out
1142 
         gt0_txoutclkpcs_out
1143
1144
1145 
         gt0_txgearboxready_out
1146 
         gt0_txgearboxready_out
1147
1148
1149 
         gt0_txheader_in[2:0]
1150 
         gt0_txheader_in[2:0]
1151
1152
1153 
         gt0_txstartseq_in
1154 
         gt0_txstartseq_in
1155
1156
1157 
         gt0_txresetdone_out
1158 
         gt0_txresetdone_out
1159
1160
1161 
         GT0_QPLLLOCK_OUT
1162 
         GT0_QPLLLOCK_OUT
1163
1164
1165 
         GT0_QPLLREFCLKLOST_OUT
1166 
         GT0_QPLLREFCLKLOST_OUT
1167
1168
1169 
         GT0_QPLLOUTCLK_OUT
1170 
         GT0_QPLLOUTCLK_OUT
1171
1172
1173 
         GT0_QPLLOUTREFCLK_OUT
1174 
         GT0_QPLLOUTREFCLK_OUT
1175
1176
1177 
         sysclk_in
1178 
         sysclk_in
1179
1180
1181
1182 
      InterlakenRX
1183 
      label
1184
1185
1186 
         fifo_read_clk
1187 
         fifo_read_clk
1188
1189
1190 
         clk
1191 
         clk
1192
1193
1194 
         reset
1195 
         reset
1196
1197
1198 
         RX_Data_In[66:0]
1199 
         RX_Data_In[66:0]
1200
1201
1202 
         RX_Data_Out[63:0]
1203 
         RX_Data_Out[63:0]
1204
1205
1206 
         RX_Enable
1207 
         RX_Enable
1208
1209
1210 
         RX_SOP
1211 
         RX_SOP
1212
1213
1214 
         RX_ValidBytes[2:0]
1215 
         RX_ValidBytes[2:0]
1216
1217
1218 
         RX_EOP
1219 
         RX_EOP
1220
1221
1222 
         RX_FlowControl[15:0]
1223 
         RX_FlowControl[15:0]
1224
1225
1226 
         RX_prog_full[15:0]
1227 
         RX_prog_full[15:0]
1228
1229
1230 
         RX_Channel[7:0]
1231 
         RX_Channel[7:0]
1232
1233
1234 
         RX_Datavalid
1235 
         RX_Datavalid
1236
1237
1238 
         CRC24_Error
1239 
         CRC24_Error
1240
1241
1242 
         CRC32_Error
1243 
         CRC32_Error
1244
1245
1246 
         Decoder_lock
1247 
         Decoder_lock
1248
1249
1250 
         Descrambler_lock
1251 
         Descrambler_lock
1252
1253
1254 
         FIFO_Full
1255 
         FIFO_Full
1256
1257
1258 
         FIFO_empty
1259 
         FIFO_empty
1260
1261
1262 
         RX_Link_Up
1263 
         RX_Link_Up
1264
1265
1266 
         Bitslip
1267 
         Bitslip
1268
1269
1270 
         pres_state
1271 
         pres_state
1272
1273
1274 
         next_state
1275 
         next_state
1276
1277
1278 
         RX_FIFO_Data[65:0]
1279 
         RX_FIFO_Data[65:0]
1280 
         #808000
1281 
         true
1282
1283
1284 
         RX_FIFO_Write
1285 
         RX_FIFO_Write
1286 
         #808000
1287 
         true
1288
1289
1290 
         FIFO_Read_Count[5:0]
1291 
         FIFO_Read_Count[5:0]
1292 
         #808000
1293 
         true
1294
1295
1296 
         FIFO_Write_Count[5:0]
1297 
         FIFO_Write_Count[5:0]
1298 
         #808000
1299 
         true
1300
1301
1302 
         FIFO_prog_full
1303 
         FIFO_prog_full
1304 
         #808000
1305 
         true
1306
1307
1308 
         FIFO_prog_empty
1309 
         FIFO_prog_empty
1310 
         #808000
1311 
         true
1312
1313
1314 
         FIFO_Data_Out[65:0]
1315 
         FIFO_Data_Out[65:0]
1316 
         #808000
1317 
         true
1318
1319
1320 
         Data_Burst_Out[65:0]
1321 
         Data_Burst_Out[65:0]
1322
1323
1324 
         Data_valid_Burst_Out
1325 
         Data_valid_Burst_Out
1326
1327
1328 
         Flowcontrol[15:0]
1329 
         Flowcontrol[15:0]
1330
1331
1332 
         Data_Descrambler_Out[63:0]
1333 
         Data_Descrambler_Out[63:0]
1334 
         #FFD700
1335 
         true
1336
1337
1338 
         Data_valid_Descrambler_out
1339 
         Data_valid_Descrambler_out
1340 
         #FFD700
1341 
         true
1342
1343
1344 
         Data_Control_Descrambler_Out
1345 
         Data_Control_Descrambler_Out
1346 
         #FFD700
1347 
         true
1348
1349
1350 
         Data_Meta_Out[63:0]
1351 
         Data_Meta_Out[63:0]
1352
1353
1354 
         Data_valid_Meta_out
1355 
         Data_valid_Meta_out
1356
1357
1358 
         Data_control_Meta_out
1359 
         Data_control_Meta_out
1360
1361
1362 
         Data_Decoder_Out[63:0]
1363 
         Data_Decoder_Out[63:0]
1364
1365
1366 
         Data_Control_Decoder_Out
1367 
         Data_Control_Decoder_Out
1368
1369
1370 
         Data_valid_decoder_out
1371 
         Data_valid_decoder_out
1372
1373
1374 
         Lane_Number[3:0]
1375 
         Lane_Number[3:0]
1376
1377
1378 
         Error_BadSync
1379 
         Error_BadSync
1380
1381
1382 
         Error_StateMismatch
1383 
         Error_StateMismatch
1384
1385
1386 
         Error_NoSync
1387 
         Error_NoSync
1388
1389
1390 
         Error_Decoder_Sync
1391 
         Error_Decoder_Sync
1392
1393
1394 
         Descrambler_In_lock
1395 
         Descrambler_In_lock
1396
1397
1398 
         PacketLength
1399 
         PacketLength
1400
1401
1402
1403 
      Decoder
1404 
      label
1405
1406 
         Clk
1407 
         Clk
1408
1409
1410 
         Reset
1411 
         Reset
1412
1413
1414 
         Data_In[66:0]
1415 
         Data_In[66:0]
1416
1417
1418 
         Decoder_En
1419 
         Decoder_En
1420
1421
1422 
         Data_Valid_In
1423 
         Data_Valid_In
1424
1425
1426 
         Data_Valid_Out
1427 
         Data_Valid_Out
1428
1429
1430 
         Data_Out[63:0]
1431 
         Data_Out[63:0]
1432
1433
1434 
         Data_Control
1435 
         Data_Control
1436
1437
1438 
         Sync_Locked
1439 
         Sync_Locked
1440
1441
1442 
         Sync_Error
1443 
         Sync_Error
1444
1445
1446 
         Bitslip
1447 
         Bitslip
1448
1449
1450 
         pres_state
1451 
         pres_state
1452
1453
1454 
         next_state
1455 
         next_state
1456
1457
1458 
         Data_T1[66:0]
1459 
         Data_T1[66:0]
1460
1461
1462 
         Data_T2[66:0]
1463 
         Data_T2[66:0]
1464
1465
1466 
         Data_T3[66:0]
1467 
         Data_T3[66:0]
1468
1469
1470 
         Data_Valid_P1
1471 
         Data_Valid_P1
1472
1473
1474 
         Data_Valid_P2
1475 
         Data_Valid_P2
1476
1477
1478 
         Data_Valid_P3
1479 
         Data_Valid_P3
1480
1481
1482 
         Data_P1[66:0]
1483 
         Data_P1[66:0]
1484
1485
1486 
         Data_P2[66:0]
1487 
         Data_P2[66:0]
1488
1489
1490 
         Data_P3[66:0]
1491 
         Data_P3[66:0]
1492
1493
1494 
         Sync_Transition_Location
1495 
         Sync_Transition_Location
1496
1497
1498 
         Sync_Search
1499 
         Sync_Search
1500
1501
1502 
         Sync_Counter
1503 
         Sync_Counter
1504
1505
1506 
         Word_Counter
1507 
         Word_Counter
1508
1509
1510 
         Sync_Error_Counter
1511 
         Sync_Error_Counter
1512
1513
1514 
         Trans_result
1515 
         Trans_result
1516
1517
1518
1519 
      Descrambler
1520 
      label
1521
1522
1523 
         Clk
1524 
         Clk
1525
1526
1527 
         Reset
1528 
         Reset
1529
1530
1531 
         Data_In[63:0]
1532 
         Data_In[63:0]
1533
1534
1535 
         Data_Valid_In
1536 
         Data_Valid_In
1537
1538
1539 
         Data_Control_In
1540 
         Data_Control_In
1541
1542
1543 
         Data_Out[63:0]
1544 
         Data_Out[63:0]
1545
1546
1547 
         Data_Valid_Out
1548 
         Data_Valid_Out
1549
1550
1551 
         Data_Control_Out
1552 
         Data_Control_Out
1553
1554
1555 
         Lane_Number[3:0]
1556 
         Lane_Number[3:0]
1557
1558
1559 
         Lock
1560 
         Lock
1561
1562
1563 
         Error_BadSync
1564 
         Error_BadSync
1565
1566
1567 
         Error_StateMismatch
1568 
         Error_StateMismatch
1569
1570
1571 
         Error_NoSync
1572 
         Error_NoSync
1573
1574
1575 
         pres_state
1576 
         pres_state
1577
1578
1579 
         next_state
1580 
         next_state
1581
1582
1583 
         MetaCounter
1584 
         MetaCounter
1585
1586
1587 
         Sync_Word_Detected
1588 
         Sync_Word_Detected
1589
1590
1591 
         Sync_Words
1592 
         Sync_Words
1593
1594
1595 
         Data_Valid_P1
1596 
         Data_Valid_P1
1597
1598
1599 
         Data_Valid_P2
1600 
         Data_Valid_P2
1601
1602
1603 
         Data_Valid
1604 
         Data_Valid
1605
1606
1607 
         Data_Control_P1
1608 
         Data_Control_P1
1609
1610
1611 
         Data_Control_P2
1612 
         Data_Control_P2
1613
1614
1615 
         Data_Control
1616 
         Data_Control
1617
1618
1619 
         Data_P1[63:0]
1620 
         Data_P1[63:0]
1621
1622
1623 
         Data_Descrambled[63:0]
1624 
         Data_Descrambled[63:0]
1625
1626
1627 
         Scrambler_State_Mismatch
1628 
         Scrambler_State_Mismatch
1629
1630
1631 
         Sync_Word_Mismatch
1632 
         Sync_Word_Mismatch
1633
1634
1635 
         Poly[57:0]
1636 
         Poly[57:0]
1637
1638
1639 
         Shiftreg[63:0]
1640 
         Shiftreg[63:0]
1641
1642
1643 
         PacketLength
1644 
         PacketLength
1645
1646
1647
1648 
      Deframing_Meta
1649 
      label
1650
1651 
         Clk
1652 
         Clk
1653
1654
1655 
         Reset
1656 
         Reset
1657
1658
1659 
         Deframer_En
1660 
         Deframer_En
1661
1662
1663 
         Data_In[63:0]
1664 
         Data_In[63:0]
1665
1666
1667 
         Data_Out[63:0]
1668 
         Data_Out[63:0]
1669
1670
1671 
         Data_Control_In
1672 
         Data_Control_In
1673
1674
1675 
         Data_Control_Out
1676 
         Data_Control_Out
1677
1678
1679 
         CRC32_Error
1680 
         CRC32_Error
1681
1682
1683 
         Data_Valid_In
1684 
         Data_Valid_In
1685
1686
1687 
         Data_Valid_Out
1688 
         Data_Valid_Out
1689
1690
1691 
         pres_state
1692 
         pres_state
1693
1694
1695 
         next_state
1696 
         next_state
1697
1698
1699 
         Packet_Counter
1700 
         Packet_Counter
1701
1702
1703 
         Data_P1[63:0]
1704 
         Data_P1[63:0]
1705
1706
1707 
         Data_P2[63:0]
1708 
         Data_P2[63:0]
1709
1710
1711 
         Data_P3[63:0]
1712 
         Data_P3[63:0]
1713
1714
1715 
         Diagnostic_Error
1716 
         Diagnostic_Error
1717
1718
1719 
         CRC32_Value[31:0]
1720 
         CRC32_Value[31:0]
1721
1722
1723 
         HealthLane
1724 
         HealthLane
1725
1726
1727 
         HealthInterface
1728 
         HealthInterface
1729
1730
1731 
         CRC32_In[63:0]
1732 
         CRC32_In[63:0]
1733
1734
1735 
         CRC32_Out[31:0]
1736 
         CRC32_Out[31:0]
1737
1738
1739 
         CRC32_En
1740 
         CRC32_En
1741
1742
1743 
         CRC32_Rst
1744 
         CRC32_Rst
1745
1746
1747 
         CrcCalc
1748 
         CrcCalc
1749
1750
1751 
         CRC32_Check1
1752 
         CRC32_Check1
1753
1754
1755 
         CRC32_Check2
1756 
         CRC32_Check2
1757
1758
1759 
         CRC32_Good
1760 
         CRC32_Good
1761
1762
1763
1764 
      Deframing_Burst
1765 
      label
1766
1767
1768 
         Clk
1769 
         Clk
1770
1771
1772 
         Reset
1773 
         Reset
1774
1775
1776 
         Deburst_En
1777 
         Deburst_En
1778
1779
1780 
         Data_In[63:0]
1781 
         Data_In[63:0]
1782
1783
1784 
         Data_Control_In
1785 
         Data_Control_In
1786
1787
1788 
         Data_Valid_In
1789 
         Data_Valid_In
1790
1791
1792 
         Data_Out[65:0]
1793 
         Data_Out[65:0]
1794 
         #FFD700
1795 
         true
1796
1797
1798 
         Data_Valid_Out
1799 
         Data_Valid_Out
1800 
         #FFD700
1801 
         true
1802
1803
1804 
         CRC24_Error
1805 
         CRC24_Error
1806
1807
1808 
         Flowcontrol[15:0]
1809 
         Flowcontrol[15:0]
1810
1811
1812 
         pres_state
1813 
         pres_state
1814
1815
1816 
         next_state
1817 
         next_state
1818
1819
1820 
         Packet_Counter
1821 
         Packet_Counter
1822
1823
1824 
         Data_P1[65:0]
1825 
         Data_P1[65:0]
1826
1827
1828 
         Data_P2[65:0]
1829 
         Data_P2[65:0]
1830
1831
1832 
         Data_P3[65:0]
1833 
         Data_P3[65:0]
1834
1835
1836 
         Data_Temp[65:0]
1837 
         Data_Temp[65:0]
1838
1839
1840 
         CRC24_Value[31:0]
1841 
         CRC24_Value[31:0]
1842
1843
1844 
         CRC24_Value_P1[31:0]
1845 
         CRC24_Value_P1[31:0]
1846
1847
1848 
         SOP
1849 
         SOP
1850
1851
1852 
         EOP
1853 
         EOP
1854
1855
1856 
         EOP_Valid[2:0]
1857 
         EOP_Valid[2:0]
1858
1859
1860 
         Channel[7:0]
1861 
         Channel[7:0]
1862
1863
1864 
         CRC24_In[63:0]
1865 
         CRC24_In[63:0]
1866
1867
1868 
         CRC24_Out[31:0]
1869 
         CRC24_Out[31:0]
1870
1871
1872 
         CRC24_En
1873 
         CRC24_En
1874
1875
1876 
         CRC24_Rst
1877 
         CRC24_Rst
1878
1879
1880 
         ILA
1881 
         label
1882
1883
1884 
            clk
1885 
            clk
1886
1887
1888 
            probe0[63:0]
1889 
            probe0[63:0]
1890
1891
1892 
            probe1[4:0]
1893 
            probe1[4:0]
1894
1895
1896 
            probe2[63:0]
1897 
            probe2[63:0]
1898
1899
1900 
            probe3[4:0]
1901 
            probe3[4:0]
1902
1903
1904
1905

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.