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N.Boukadid |
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Decoder is
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port(
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Clk : in std_logic; -- Clock input
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Reset : in std_logic; -- Reset decoder
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Data_In : in std_logic_vector(66 downto 0); -- Data input
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Decoder_En : in std_logic; -- Enables the decoder
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Data_Valid_In : in std_logic;
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Data_Valid_Out : out std_logic;
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Data_Out : out std_logic_vector(66 downto 0);-- Decoded 64-bit output
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Data_Control : out std_logic; -- Indicates whether the word is data or control
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Sync_Locked : out std_logic;
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Sync_Error : out std_logic;
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Bitslip : out std_logic
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);
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end entity Decoder;
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architecture Decoding of Decoder is
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type state_type is (IDLE, SYNC, LOCKED);
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signal pres_state, next_state : state_type;
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signal Data_T1, Data_T2, Data_T3 : std_logic_vector(66 downto 0);
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--shared variable Sync_ChangeCounter : integer range 0 to 65; -- Counts common bit changes
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signal Data_Valid_P1, Data_Valid_P2, Data_Valid_P3 : std_logic;
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signal Data_P1, Data_P2, Data_P3 : std_logic_vector(66 downto 0);
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signal Sync_Transition_Location : integer := 0;
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signal Sync_Search : std_logic;
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signal Sync_Counter, Word_Counter : integer range 0 to 65;
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signal Sync_Error_Counter : integer range 0 to 17;
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signal Trans_result : integer range 0 to 65;
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begin
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input : process (Clk, Reset) is --Input registers/pipelining
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begin
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if (Reset = '1') then
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Data_P1 <= (others => '1');
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Data_P2 <= (others => '1');
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Data_P3 <= (others => '1');
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elsif (rising_edge(clk)) then
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Data_P3 <= Data_P2;
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Data_P2 <= Data_P1;
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Data_Valid_P3 <= Data_Valid_P2;
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Data_Valid_P2 <= Data_Valid_P1;
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if (Data_Valid_In = '1') then
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Data_P1(66 downto 64) <= Data_In(66 downto 64);
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Data_P1(63 downto 0) <= Data_In(63 downto 0);
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Data_Valid_P1 <= '1';
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else
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Data_P1 <= Data_P1;
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Data_Valid_P1 <= '0';
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end if;
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end if;
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end process input;
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transitions : process (Clk, Reset) is -- Detect transitions to locate the preamble
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begin
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if (Reset = '1') then
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Data_T1 <= (others => '1');
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Data_T2 <= (others => '1');
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elsif (rising_edge(clk)) then
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for i in 66 downto 1 loop -- Indicates bit transitions of incoming data
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Data_T1(i) <= (Data_P1(i) xor Data_P1(i-1));
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end loop;
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Data_T1(0) <= '0'; -- Last bit must be zero
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Data_T2 <= Data_T1 and Data_T2; -- Loop and compare to new data, only the transitions always occuring will be left
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if Data_T1 = (Data_T1'range => '0') or Data_T2 = (Data_T2'range => '0') then
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Data_T2 <= (others => '1');
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end if;
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end if;
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end process transitions;
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synchronize : process (Clk, Reset, Sync_Search, Data_T2) is --Locate the preamble according to the detected transitions
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variable Sync_TransitionCounter: integer range 0 to 65 := 0; -- Counts common bit transitions
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begin
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if (Reset = '1') then
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Sync_TransitionCounter := 0;
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elsif (rising_edge(clk)) then
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Sync_TransitionCounter := 0;
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if (Sync_Search = '1') then
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Sync_TransitionCounter := 0;
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for j in 66 downto 0 loop -- Count transitions that occur
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if(Data_T2(j) = '1') then
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Sync_TransitionCounter := Sync_TransitionCounter + 1;
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Sync_Transition_Location <= j;
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else
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Sync_TransitionCounter := Sync_TransitionCounter;
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end if;
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end loop;
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end if;
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Trans_result <= Sync_TransitionCounter;
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end if;
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end process synchronize;
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state_register : process (clk) is
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begin
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if (rising_edge(clk)) then
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pres_state <= next_state;
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end if;
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end process state_register;
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state_decoder : process (pres_state, Decoder_En, Sync_Counter, Sync_Error_Counter, Trans_result, Sync_Transition_Location) is
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begin
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case pres_state is
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when IDLE =>
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if (Decoder_En = '1' and Trans_result < 67) then
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next_state <= SYNC;
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else
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next_state <= IDLE;
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end if;
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when SYNC =>
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if(Sync_Counter >= 63 and Trans_result = 1 and Sync_Transition_Location = 65) then
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next_state <= Locked;
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elsif (Trans_result = 0) then
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next_state <= IDLE;
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else
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next_state <= SYNC;
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end if;
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when LOCKED =>
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if (Sync_Error_Counter > 14) then
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next_state <= IDLE;
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else
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next_state <= LOCKED;
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end if;
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when others =>
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next_state <= IDLE;
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end case;
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end process state_decoder;
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output : process (pres_state, clk) is
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variable Data_Temp : std_logic_vector(63 downto 0);
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variable Data_Lock : std_logic_vector(66 downto 0);
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variable Data_Header : std_logic_vector(2 downto 0);
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variable shift_timeout : integer range 0 to 63;
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begin
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if rising_edge(clk) then
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Bitslip <= '0';
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case pres_state is
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when IDLE =>
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Sync_Error <= '0';
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Sync_Locked <= '0';
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Sync_Search <= '1';
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Sync_Counter <= 0;
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Data_Control <= '0';
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Data_T3 <= (others => '0');
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Data_Lock := (others => '0');
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Data_Out <= (others => '0');
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-- if (Decoder_En = '1' and Sync_TransitionCounter < 67) then
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-- Sync_Counter <= 1;
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-- end if;
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when SYNC =>
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if (Data_Valid_In = '1') then
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Sync_Counter <= Sync_Counter + 1; --Count sync words passed
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if(Sync_Counter >= 63 and Trans_result = 1 and Sync_Transition_Location = 65) then
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Data_Lock := Data_T2; -- If decoder goes in lock, data including bit position will be saved
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Sync_Counter <= 0 ; -- Reset counter after changing state
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Sync_Locked <= '1';
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Sync_Search <= '0';
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Data_Control <= '1';
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Data_T3 <= Data_Lock and Data_T1;
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elsif (Trans_result = 0) then
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Sync_Error <= '1';
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end if;
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if (Sync_Transition_Location /= 65) then
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if(shift_timeout = 0) then
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Bitslip <= '1';
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shift_timeout := 63;
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else
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shift_timeout := shift_timeout - 1;
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Bitslip <= '0';
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end if;
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else
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Bitslip <= '0';
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end if;
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end if;
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when LOCKED =>
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Sync_Locked <= '1';
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Sync_Error <= '0';
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Word_Counter <= Word_Counter + 1; -- Count data words passed
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Data_T3 <= Data_Lock and Data_T1;
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if(Data_T3(Sync_Transition_Location) = '0') then
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Sync_Error_Counter <= Sync_Error_Counter + 1;
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Sync_Error <= '1';
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Data_out <= (others => '0');
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Data_Header := "010";
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else
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--Change to P2!!!
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Data_Temp := Data_P3(63 downto 0);
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Data_Header := Data_P3(66 downto 64);
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end if;
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Data_Valid_Out <= Data_Valid_P3;
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if (Data_Header(2) = '1') then -- Read inversion bit
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Data_Out(63 downto 0) <= not(Data_Temp(63 downto 0));
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else
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Data_Out(63 downto 0) <= Data_Temp(63 downto 0);
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end if;
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Data_Out(66 downto 64) <= Data_Header;
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if(Data_Header(1) = '1') then -- Read control word bit
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Data_Control <= '1';
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else
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Data_Control <= '0';
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end if;
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if (Sync_Error_Counter > 14) then -- Rest error counter after 16 errors
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Sync_Locked <= '0';
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Sync_Error_Counter <= 0;
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end if;
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if (Word_Counter > 63) then -- Reset word and error counters after 64 passed words
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Word_Counter <= 1;
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Sync_Error_Counter <= 0;
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end if;
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end case;
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end if;
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end process output;
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end architecture Decoding;
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