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Subversion Repositories core1990_interlaken

[/] [core1990_interlaken/] [trunk/] [gateware/] [sources/] [ip_cores/] [vc709/] [clk_40MHz.xci] - Blame information for rev 11

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  xilinx.com
  xci
  unknown
  1.0
  
    
      clk_40MHz
      
      
        false
        100000000
        false
        100000000
        false
        100000000
        false
        100000000
        
        
        
        100000000
        0
        0.000
        
        
        
        100000000
        0
        0.000
        1
        LEVEL_HIGH
        
        
        
        100000000
        0
        0.000
        0
        0
        
        100000000
        0
        0.000
        1
        0
        0
        0
        
        1
        100000000
        0
        0
        0
        0
        0
        0
        0
        0
        0
        0
        0
        1
        1
        1
        1
        1
        0.000
        AXI4LITE
        READ_WRITE
        0
        0
        0
        0
        0
        0
        MMCM
        cddcdone
        cddcreq
        0000
        0000
        clkfb_in_n
        clkfb_in
        clkfb_in_p
        SINGLE
        clkfb_out_n
        clkfb_out
        clkfb_out_p
        clkfb_stopped
        50.0
        40.0
        0000
        0000
        40.000
        0000
        0000
        150.000
        BUFG
        50.0
        false
        40.000
        0.000
        50.000
        40.000
        0.000
        1
        0000
        0000
        100.000
        BUFG
        50.0
        false
        150.000
        0.000
        50.000
        150.000
        0.000
        1
        1
        0000
        0000
        100.000
        BUFG
        50.000
        false
        100.000
        0.000
        50.000
        100.000
        0.000
        1
        0
        0000
        0000
        100.000
        BUFG
        50.000
        false
        100.000
        0.000
        50.000
        100.000
        0.000
        1
        0
        0000
        0000
        100.000
        BUFG
        50.000
        false
        100.000
        0.000
        50.000
        100.000
        0.000
        1
        0
        0000
        0000
        100.000
        BUFG
        50.000
        false
        100.000
        0.000
        50.000
        100.000
        0.000
        1
        0
        BUFG
        50.000
        false
        100.000
        0.000
        50.000
        100.000
        0.000
        1
        0
        VCO
        clk_in_sel
        clk_out1
        clk_out2
        clk_out3
        clk_out4
        clk_out5
        clk_out6
        clk_out7
        CLK_VALID
        NA
        daddr
        dclk
        den
        din
        0000
        1
        0.26666666666666666
        0.4
        0.4
        0.4
        0.4
        0.4
        dout
        drdy
        dwe
        0
        0
        0
        0
        0
        0
        0
        0
        FDBK_AUTO
        0000
        0000
        0
        Input Clock   Freq (MHz)    Input Jitter (UI)
        __primary_________200.000____________0.010
        no_secondary_input_clock 
        input_clk_stopped
        0
        Units_MHz
        No_Jitter
        locked
        0000
        0000
        0000
        false
        false
        false
        false
        false
        false
        false
        false
        OPTIMIZED
        5.250
        0.000
        FALSE
        5.000
        10.0
        26.250
        0.500
        0.000
        FALSE
        7
        0.500
        0.000
        FALSE
        1
        0.500
        0.000
        FALSE
        1
        0.500
        0.000
        FALSE
        FALSE
        1
        0.500
        0.000
        FALSE
        1
        0.500
        0.000
        FALSE
        1
        0.500
        0.000
        FALSE
        FALSE
        ZHOLD
        1
        None
        0.010
        0.010
        FALSE
        2
         Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
          Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
        clk_out1____40.000______0.000______50.0______132.550_____87.375
        clk_out2___150.000______0.000______50.0______101.763_____87.375
        no_CLK_OUT3_output
        no_CLK_OUT4_output
        no_CLK_OUT5_output
        no_CLK_OUT6_output
        no_CLK_OUT7_output
        0
        0
        WAVEFORM
        UNKNOWN
        false
        false
        false
        false
        false
        OPTIMIZED
        1
        0.000
        1.000
        1
        0.500
        0.000
        1
        0.500
        0.000
        1
        0.500
        0.000
        1
        0.500
        0.000
        1
        0.500
        0.000
        1
        0.500
        0.000
        CLKFBOUT
        SYSTEM_SYNCHRONOUS
        1
        No notes
        0.010
        power_down
        0000
        1
        clk_in1
        MMCM
        AUTO
        200.000
        0.010
        10.000
        Differential_clock_capable_pin
        psclk
        psdone
        psen
        psincdec
        100.0
        0
        reset
        100.000
        0.010
        10.000
        clk_in2
        Single_ended_clock_capable_pin
        CENTER_HIGH
        4000
        0.004
        STATUS
        11
        32
        100.0
        100.0
        100.0
        100.0
        0
        0
        0
        0
        0
        0
        0
        0
        0
        0
        0
        1
        0
        0
        1
        0
        0
        0
        1
        0
        1
        0
        0
        0
        clk_40MHz
        MMCM
        false
        empty
        cddcdone
        cddcreq
        clkfb_in_n
        clkfb_in
        clkfb_in_p
        SINGLE
        clkfb_out_n
        clkfb_out
        clkfb_out_p
        clkfb_stopped
        50.0
        0.010
        40.0
        0.010
        BUFG
        132.550
        false
        87.375
        50.000
        40.000
        0.000
        1
        true
        BUFG
        101.763
        false
        87.375
        50.000
        150.000
        0.000
        1
        true
        BUFG
        0.0
        false
        0.0
        50.000
        100.000
        0.000
        1
        false
        BUFG
        0.0
        false
        0.0
        50.000
        100.000
        0.000
        1
        false
        BUFG
        0.0
        false
        0.0
        50.000
        100.000
        0.000
        1
        false
        BUFG
        0.0
        false
        0.0
        50.000
        100.000
        0.000
        1
        false
        BUFG
        0.0
        false
        0.0
        50.000
        100.000
        0.000
        1
        false
        600.000
        sys_diff_clock
        Custom
        clk_in_sel
        clk_out1
        false
        clk_out2
        false
        clk_out3
        false
        clk_out4
        false
        clk_out5
        false
        clk_out6
        false
        clk_out7
        false
        CLK_VALID
        auto
        clk_40MHz
        daddr
        dclk
        den
        Custom
        Custom
        din
        dout
        drdy
        dwe
        false
        false
        false
        false
        false
        false
        false
        false
        false
        FDBK_AUTO
        input_clk_stopped
        frequency
        Enable_AXI
        Units_MHz
        Units_UI
        UI
        No_Jitter
        locked
        OPTIMIZED
        5.250
        0.000
        false
        5.000
        10.0
        26.250
        0.500
        0.000
        false
        7
        0.500
        0.000
        false
        1
        0.500
        0.000
        false
        1
        0.500
        0.000
        false
        false
        1
        0.500
        0.000
        false
        1
        0.500
        0.000
        false
        1
        0.500
        0.000
        false
        false
        ZHOLD
        1
        None
        0.010
        0.010
        false
        2
        false
        false
        WAVEFORM
        false
        UNKNOWN
        OPTIMIZED
        4
        0.000
        10.000
        1
        0.500
        0.000
        1
        0.500
        0.000
        1
        0.500
        0.000
        1
        0.500
        0.000
        1
        0.500
        0.000
        1
        0.500
        0.000
        CLKFBOUT
        SYSTEM_SYNCHRONOUS
        1
        None
        0.010
        power_down
        1
        clk_in1
        MMCM
        mmcm_adv
        200.000
        0.010
        10.000
        Differential_clock_capable_pin
        psclk
        psdone
        psen
        psincdec
        100.0
        REL_PRIMARY
        Custom
        reset
        ACTIVE_HIGH
        100.000
        0.010
        10.000
        clk_in2
        Single_ended_clock_capable_pin
        CENTER_HIGH
        250
        0.004
        STATUS
        empty
        100.0
        100.0
        100.0
        100.0
        false
        false
        false
        false
        false
        false
        false
        true
        false
        false
        true
        false
        false
        false
        true
        false
        true
        false
        false
        false
        virtex7
        
        
        xc7vx690t
        ffg1761
        VHDL
        
        MIXED
        -2
        
        
        TRUE
        TRUE
        IP_Flow
        3
        TRUE
        .
        
        .
        2019.1
        OUT_OF_CONTEXT
      
      
        
          
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
          
        
      
    
  


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Subversion Repositories core1990_interlaken

[/] [core1990_interlaken/] [trunk/] [gateware/] [sources/] [ip_cores/] [vc709/] [clk_40MHz.xci] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	N.Boukadid
2
3			`xilinx.com`
4			`xci`
5			`unknown`
6			`1.0`
7
8
9			`clk_40MHz`
10
11
12			`false`
13			`100000000`
14			`false`
15			`100000000`
16			`false`
17			`100000000`
18			`false`
19			`100000000`
20
21
22
23			`100000000`
24			`0`
25			`0.000`
26
27
28
29			`100000000`
30			`0`
31			`0.000`
32			`1`
33			`LEVEL_HIGH`
34
35
36
37			`100000000`
38			`0`
39			`0.000`
40			`0`
41			`0`
42
43			`100000000`
44			`0`
45			`0.000`
46			`1`
47			`0`
48			`0`
49			`0`
50
51			`1`
52			`100000000`
53			`0`
54			`0`
55			`0`
56			`0`
57			`0`
58			`0`
59			`0`
60			`0`
61			`0`
62			`0`
63			`0`
64			`1`
65			`1`
66			`1`
67			`1`
68			`1`
69			`0.000`
70			`AXI4LITE`
71			`READ_WRITE`
72			`0`
73			`0`
74			`0`
75			`0`
76			`0`
77			`0`
78			`MMCM`
79			`cddcdone`
80			`cddcreq`
81			`0000`
82			`0000`
83			`clkfb_in_n`
84			`clkfb_in`
85			`clkfb_in_p`
86			`SINGLE`
87			`clkfb_out_n`
88			`clkfb_out`
89			`clkfb_out_p`
90			`clkfb_stopped`
91			`50.0`
92			`40.0`
93			`0000`
94			`0000`
95			`40.000`
96			`0000`
97			`0000`
98			`150.000`
99			`BUFG`
100			`50.0`
101			`false`
102			`40.000`
103			`0.000`
104			`50.000`
105			`40.000`
106			`0.000`
107			`1`
108			`0000`
109			`0000`
110			`100.000`
111			`BUFG`
112			`50.0`
113			`false`
114			`150.000`
115			`0.000`
116			`50.000`
117			`150.000`
118			`0.000`
119			`1`
120			`1`
121			`0000`
122			`0000`
123			`100.000`
124			`BUFG`
125			`50.000`
126			`false`
127			`100.000`
128			`0.000`
129			`50.000`
130			`100.000`
131			`0.000`
132			`1`
133			`0`
134			`0000`
135			`0000`
136			`100.000`
137			`BUFG`
138			`50.000`
139			`false`
140			`100.000`
141			`0.000`
142			`50.000`
143			`100.000`
144			`0.000`
145			`1`
146			`0`
147			`0000`
148			`0000`
149			`100.000`
150			`BUFG`
151			`50.000`
152			`false`
153			`100.000`
154			`0.000`
155			`50.000`
156			`100.000`
157			`0.000`
158			`1`
159			`0`
160			`0000`
161			`0000`
162			`100.000`
163			`BUFG`
164			`50.000`
165			`false`
166			`100.000`
167			`0.000`
168			`50.000`
169			`100.000`
170			`0.000`
171			`1`
172			`0`
173			`BUFG`
174			`50.000`
175			`false`
176			`100.000`
177			`0.000`
178			`50.000`
179			`100.000`
180			`0.000`
181			`1`
182			`0`
183			`VCO`
184			`clk_in_sel`
185			`clk_out1`
186			`clk_out2`
187			`clk_out3`
188			`clk_out4`
189			`clk_out5`
190			`clk_out6`
191			`clk_out7`
192			`CLK_VALID`
193			`NA`
194			`daddr`
195			`dclk`
196			`den`
197			`din`
198			`0000`
199			`1`
200			`0.26666666666666666`
201			`0.4`
202			`0.4`
203			`0.4`
204			`0.4`
205			`0.4`
206			`dout`
207			`drdy`
208			`dwe`
209			`0`
210			`0`
211			`0`
212			`0`
213			`0`
214			`0`
215			`0`
216			`0`
217			`FDBK_AUTO`
218			`0000`
219			`0000`
220			`0`
221			`Input Clock Freq (MHz) Input Jitter (UI)`
222			`__primary_________200.000____________0.010`
223			`no_secondary_input_clock`
224			`input_clk_stopped`
225			`0`
226			`Units_MHz`
227			`No_Jitter`
228			`locked`
229			`0000`
230			`0000`
231			`0000`
232			`false`
233			`false`
234			`false`
235			`false`
236			`false`
237			`false`
238			`false`
239			`false`
240			`OPTIMIZED`
241			`5.250`
242			`0.000`
243			`FALSE`
244			`5.000`
245			`10.0`
246			`26.250`
247			`0.500`
248			`0.000`
249			`FALSE`
250			`7`
251			`0.500`
252			`0.000`
253			`FALSE`
254			`1`
255			`0.500`
256			`0.000`
257			`FALSE`
258			`1`
259			`0.500`
260			`0.000`
261			`FALSE`
262			`FALSE`
263			`1`
264			`0.500`
265			`0.000`
266			`FALSE`
267			`1`
268			`0.500`
269			`0.000`
270			`FALSE`
271			`1`
272			`0.500`
273			`0.000`
274			`FALSE`
275			`FALSE`
276			`ZHOLD`
277			`1`
278			`None`
279			`0.010`
280			`0.010`
281			`FALSE`
282			`2`
283			`Output Output Phase Duty Cycle Pk-to-Pk Phase`
284			`Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)`
285			`clk_out1____40.000______0.000______50.0______132.550_____87.375`
286			`clk_out2___150.000______0.000______50.0______101.763_____87.375`
287			`no_CLK_OUT3_output`
288			`no_CLK_OUT4_output`
289			`no_CLK_OUT5_output`
290			`no_CLK_OUT6_output`
291			`no_CLK_OUT7_output`
292			`0`
293			`0`
294			`WAVEFORM`
295			`UNKNOWN`
296			`false`
297			`false`
298			`false`
299			`false`
300			`false`
301			`OPTIMIZED`
302			`1`
303			`0.000`
304			`1.000`
305			`1`
306			`0.500`
307			`0.000`
308			`1`
309			`0.500`
310			`0.000`
311			`1`
312			`0.500`
313			`0.000`
314			`1`
315			`0.500`
316			`0.000`
317			`1`
318			`0.500`
319			`0.000`
320			`1`
321			`0.500`
322			`0.000`
323			`CLKFBOUT`
324			`SYSTEM_SYNCHRONOUS`
325			`1`
326			`No notes`
327			`0.010`
328			`power_down`
329			`0000`
330			`1`
331			`clk_in1`
332			`MMCM`
333			`AUTO`
334			`200.000`
335			`0.010`
336			`10.000`
337			`Differential_clock_capable_pin`
338			`psclk`
339			`psdone`
340			`psen`
341			`psincdec`
342			`100.0`
343			`0`
344			`reset`
345			`100.000`
346			`0.010`
347			`10.000`
348			`clk_in2`
349			`Single_ended_clock_capable_pin`
350			`CENTER_HIGH`
351			`4000`
352			`0.004`
353			`STATUS`
354			`11`
355			`32`
356			`100.0`
357			`100.0`
358			`100.0`
359			`100.0`
360			`0`
361			`0`
362			`0`
363			`0`
364			`0`
365			`0`
366			`0`
367			`0`
368			`0`
369			`0`
370			`0`
371			`1`
372			`0`
373			`0`
374			`1`
375			`0`
376			`0`
377			`0`
378			`1`
379			`0`
380			`1`
381			`0`
382			`0`
383			`0`
384			`clk_40MHz`
385			`MMCM`
386			`false`
387			`empty`
388			`cddcdone`
389			`cddcreq`
390			`clkfb_in_n`
391			`clkfb_in`
392			`clkfb_in_p`
393			`SINGLE`
394			`clkfb_out_n`
395			`clkfb_out`
396			`clkfb_out_p`
397			`clkfb_stopped`
398			`50.0`
399			`0.010`
400			`40.0`
401			`0.010`
402			`BUFG`
403			`132.550`
404			`false`
405			`87.375`
406			`50.000`
407			`40.000`
408			`0.000`
409			`1`
410			`true`
411			`BUFG`
412			`101.763`
413			`false`
414			`87.375`
415			`50.000`
416			`150.000`
417			`0.000`
418			`1`
419			`true`
420			`BUFG`
421			`0.0`
422			`false`
423			`0.0`
424			`50.000`
425			`100.000`
426			`0.000`
427			`1`
428			`false`
429			`BUFG`
430			`0.0`
431			`false`
432			`0.0`
433			`50.000`
434			`100.000`
435			`0.000`
436			`1`
437			`false`
438			`BUFG`
439			`0.0`
440			`false`
441			`0.0`
442			`50.000`
443			`100.000`
444			`0.000`
445			`1`
446			`false`
447			`BUFG`
448			`0.0`
449			`false`
450			`0.0`
451			`50.000`
452			`100.000`
453			`0.000`
454			`1`
455			`false`
456			`BUFG`
457			`0.0`
458			`false`
459			`0.0`
460			`50.000`
461			`100.000`
462			`0.000`
463			`1`
464			`false`
465			`600.000`
466			`sys_diff_clock`
467			`Custom`
468			`clk_in_sel`
469			`clk_out1`
470			`false`
471			`clk_out2`
472			`false`
473			`clk_out3`
474			`false`
475			`clk_out4`
476			`false`
477			`clk_out5`
478			`false`
479			`clk_out6`
480			`false`
481			`clk_out7`
482			`false`
483			`CLK_VALID`
484			`auto`
485			`clk_40MHz`
486			`daddr`
487			`dclk`
488			`den`
489			`Custom`
490			`Custom`
491			`din`
492			`dout`
493			`drdy`
494			`dwe`
495			`false`
496			`false`
497			`false`
498			`false`
499			`false`
500			`false`
501			`false`
502			`false`
503			`false`
504			`FDBK_AUTO`
505			`input_clk_stopped`
506			`frequency`
507			`Enable_AXI`
508			`Units_MHz`
509			`Units_UI`
510			`UI`
511			`No_Jitter`
512			`locked`
513			`OPTIMIZED`
514			`5.250`
515			`0.000`
516			`false`
517			`5.000`
518			`10.0`
519			`26.250`
520			`0.500`
521			`0.000`
522			`false`
523			`7`
524			`0.500`
525			`0.000`
526			`false`
527			`1`
528			`0.500`
529			`0.000`
530			`false`
531			`1`
532			`0.500`
533			`0.000`
534			`false`
535			`false`
536			`1`
537			`0.500`
538			`0.000`
539			`false`
540			`1`
541			`0.500`
542			`0.000`
543			`false`
544			`1`
545			`0.500`
546			`0.000`
547			`false`
548			`false`
549			`ZHOLD`
550			`1`
551			`None`
552			`0.010`
553			`0.010`
554			`false`
555			`2`
556			`false`
557			`false`
558			`WAVEFORM`
559			`false`
560			`UNKNOWN`
561			`OPTIMIZED`
562			`4`
563			`0.000`
564			`10.000`
565			`1`
566			`0.500`
567			`0.000`
568			`1`
569			`0.500`
570			`0.000`
571			`1`
572			`0.500`
573			`0.000`
574			`1`
575			`0.500`
576			`0.000`
577			`1`
578			`0.500`
579			`0.000`
580			`1`
581			`0.500`
582			`0.000`
583			`CLKFBOUT`
584			`SYSTEM_SYNCHRONOUS`
585			`1`
586			`None`
587			`0.010`
588			`power_down`
589			`1`
590			`clk_in1`
591			`MMCM`
592			`mmcm_adv`
593			`200.000`
594			`0.010`
595			`10.000`
596			`Differential_clock_capable_pin`
597			`psclk`
598			`psdone`
599			`psen`
600			`psincdec`
601			`100.0`
602			`REL_PRIMARY`
603			`Custom`
604			`reset`
605			`ACTIVE_HIGH`
606			`100.000`
607			`0.010`
608			`10.000`
609			`clk_in2`
610			`Single_ended_clock_capable_pin`
611			`CENTER_HIGH`
612			`250`
613			`0.004`
614			`STATUS`
615			`empty`
616			`100.0`
617			`100.0`
618			`100.0`
619			`100.0`
620			`false`
621			`false`
622			`false`
623			`false`
624			`false`
625			`false`
626			`false`
627			`true`
628			`false`
629			`false`
630			`true`
631			`false`
632			`false`
633			`false`
634			`true`
635			`false`
636			`true`
637			`false`
638			`false`
639			`false`
640			`virtex7`
641
642
643			`xc7vx690t`
644			`ffg1761`
645			`VHDL`
646
647			`MIXED`
648			`-2`
649
650
651			`TRUE`
652			`TRUE`
653			`IP_Flow`
654			`3`
655			`TRUE`
656			`.`
657
658			`.`
659			`2019.1`
660			`OUT_OF_CONTEXT`
661
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665
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