Subversion Repositories cpu16

module alu (

        a,

        b,

        c_in,

        func,

        result,

        n,

        v,

        z,

        c

        );

        input [15:0] a,b;

        input c_in;

        input [2:0] func;

        output [15:0] result;

        output n,v,z,c;

        reg [15:0] addsub_result;

        reg addsub_c;

        reg addsub_v;

        always @(*)

                if ( func[1])

                        { addsub_c, addsub_result } = a + b + (c_in&func[0]);

                else

                        { addsub_c, addsub_result } = a - b - (c_in&func[0]);

        // overflow calculation

        always @(*)

                addsub_v = a[15] ^ b[15] ^ addsub_c ^ addsub_result[15];

        reg [15:0] logic_result;

        always @(*)

                case (func[1:0])

                        2'd0 : logic_result = a;                // maps to subtract

                        2'd1 : logic_result = a&b;

                        2'd2 : logic_result = a|b;

                        2'd3 : logic_result = a^b;

                endcase

        reg [15:0] result;

        always @(*)

                if ( func[2])

                        result = logic_result;

                else

                        result = addsub_result;

        reg n,v,z,c;

        always @(*)

                casex (func)

                        3'b0xx, // sub/sbc/add/adc

                        3'b100 : begin  // cmp

                                n = addsub_result[15];

                                v = addsub_v;

                                z = ~|addsub_result;

                                c = addsub_c;

                                end

                        default : begin

                                n = logic_result[15];

                                v = 1'b0;

                                z = ~|logic_result;

                                c = 1'b0;

                                end

                endcase

endmodule