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Subversion Repositories cpu6502_true_cycle

[/] [cpu6502_true_cycle/] [trunk/] [doc/] [errata.txt] - Blame information for rev 26

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v1.4 2018/09/15
FUNCTIONALITY:
 no errata reported/opened
 
TIMING:
 no errata reported/opened
 
SIGNALING:
 no errata reported/opened
 
 
v1.4 BETA 2013/07/24
FUNCTIONALITY:
- ADC and SBC in decimal mode (all op codes -
  seems to use a formula different from a real R6502.
 
TIMING:
- All Branch Instructions
  (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS)
  4 cycles if branch forward occur and the branch
  instruction lies on a xxFEh location.
  Must be 3 cycles.
 
SIGNALING:
- Hardware Interrupts NMI & IRQ - NO "SYNC"
- RESET generates NO SYNC

Line No.	Rev	Author	Line
1	26	fpga_is_fu	`v1.4 2018/09/15`
2	25	fpga_is_fu	`FUNCTIONALITY:`
3	26	fpga_is_fu	`no errata reported/opened`
4
5			`TIMING:`
6			`no errata reported/opened`
7
8			`SIGNALING:`
9			`no errata reported/opened`
10
11
12			`v1.4 BETA 2013/07/24`
13			`FUNCTIONALITY:`
14	25	fpga_is_fu	`- ADC and SBC in decimal mode (all op codes -`
15			`seems to use a formula different from a real R6502.`
16
17			`TIMING:`
18			`- All Branch Instructions`
19			`(BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS)`
20			`4 cycles if branch forward occur and the branch`
21			`instruction lies on a xxFEh location.`
22			`Must be 3 cycles.`
23
24			`SIGNALING:`
25			`- Hardware Interrupts NMI & IRQ - NO "SYNC"`
26			`- RESET generates NO SYNC`

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[/] [cpu6502_true_cycle/] [trunk/] [doc/] [errata.txt] - Blame information for rev 26