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-- VHDL Entity r6502_tc.fsm_execution_unit.symbol

--

-- Created:

--          by - eda.UNKNOWN (ENTW-7HPZ200)

--          at - 11:35:43 11.09.2018

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

entity fsm_execution_unit is

   port(

      adr_nxt_pc_i    : in     std_logic_vector (15 downto 0);

      adr_pc_i        : in     std_logic_vector (15 downto 0);

      adr_sp_i        : in     std_logic_vector (15 downto 0);

      clk_clk_i       : in     std_logic;

      d_alu_i         : in     std_logic_vector ( 7 downto 0 );

      d_i             : in     std_logic_vector ( 7 downto 0 );

      d_regs_out_i    : in     std_logic_vector ( 7 downto 0 );

      irq_n_i         : in     std_logic;

      nmi_i           : in     std_logic;

      q_a_i           : in     std_logic_vector ( 7 downto 0 );

      q_x_i           : in     std_logic_vector ( 7 downto 0 );

      q_y_i           : in     std_logic_vector ( 7 downto 0 );

      rdy_i           : in     std_logic;

      reg_0flag_i     : in     std_logic;

      reg_1flag_i     : in     std_logic;

      reg_7flag_i     : in     std_logic;

      rst_rst_n_i     : in     std_logic;

      so_n_i          : in     std_logic;

      a_o             : out    std_logic_vector (15 downto 0);

      adr_o           : out    std_logic_vector (15 downto 0);

      ch_a_o          : out    std_logic_vector ( 7 downto 0 );

      ch_b_o          : out    std_logic_vector ( 7 downto 0 );

      d_o             : out    std_logic_vector ( 7 downto 0 );

      d_regs_in_o     : out    std_logic_vector ( 7 downto 0 );

      int_fetch_o     : out    std_logic;

      int_reg_2flag_o : out    std_logic;

      ld_o            : out    std_logic_vector ( 1 downto 0 );

      ld_pc_o         : out    std_logic;

      ld_sp_o         : out    std_logic;

      load_regs_o     : out    std_logic;

      offset_o        : out    std_logic_vector ( 15 downto 0 );

      rd_o            : out    std_logic;

      rst_nmi_o       : out    std_logic;

      sel_pc_in_o     : out    std_logic;

      sel_pc_val_o    : out    std_logic_vector ( 1 downto 0 );

      sel_rb_in_o     : out    std_logic_vector ( 1 downto 0 );

      sel_rb_out_o    : out    std_logic_vector ( 1 downto 0 );

      sel_reg_o       : out    std_logic_vector ( 1 downto 0 );

      sel_sp_as_o     : out    std_logic;

      sel_sp_in_o     : out    std_logic;

      sync_o          : out    std_logic;

      wr_n_o          : out    std_logic;

      wr_o            : out    std_logic

   );

-- Declarations

end fsm_execution_unit ;

-- (C) 2008 - 2018 Jens Gutschmidt

-- (email: opencores@vivare-services.com)

-- 

-- Versions:

-- Revision 1.11  2018/09/11 11:50:00  jens

-- - RESET generates SYNC now, 1 dead cycle delayed

-- - ADC / SBC flags and A like R6502 now

-- - Bug Fix ADC and SBC in decimal mode (all op codes -

--   "Overflow" flag was computed wrong)

-- - Interrupt priority order is now: BRK - NMI - IRQ

-- - Performance improvements on-going (Mealy -> Moore)

-- - Bug Fixes All Branch Instructions 

--   (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS)

--   3 cycles now if branch forward occur and the branch

--   instruction lies on a xxFEh location.

-- - Bug Fix Hardware Interrupts NMI & IRQ - "SYNC" now

-- 

-- Revision 1.11  BETA 2013/07/24 15:46:00  jens

-- - Changing the title block and internal revision history

-- - Bug Fix ADC and SBC (all op codes - "Overflow" flag was computed wrong)

-- 

-- Revision 1.10  2010/02/08 17:34:20  eda

-- BUGFIX for IRQn, NMIn and RTI

-- After detection of NMI or IRQ the address of the next instruction stacked wrong.

-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the

-- vector address is not loaded yet.

-- 

-- Revision 1.9  2010/02/08 17:32:19  eda

-- BUGFIX for IRQn, NMIn and RTI

-- After detection of NMI or IRQ the address of the next instruction stacked wrong.

-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the

-- vector address is not loaded yet.

-- 

-- Revision 1.8  2009/01/04 20:23:42  eda

-- *** EMERGENCY BUGFIX ***

-- - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected.

-- - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist

--  when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from

--  $02FF and $0200, instead of $02FF and $0300)

-- 

-- Revision 1.7  2009/01/04 16:54:59  eda

-- - Removed unused bits in ALU (zw_ALUx)

-- 

-- Revision 1.6  2009/01/04 10:27:49  eda

-- Changes for cosmetic issues only

-- 

-- Revision 1.5  2009/01/04 10:25:04  eda

-- Changes for cosmetic issues only

-- 

-- Revision 1.4  2009/01/03 16:53:01  eda

-- - Unused nets and blocks deleted

-- - Re-arragend symbols in block FSM_Execution_Unit

-- - Renamed blocks

-- - Input SO implemented

-- 

-- Revision 1.3  2009/01/03 16:42:02  eda

-- - Unused nets and blocks deleted

-- - Re-arragend symbols in block FSM_Execution_Unit

-- - Renamed blocks

-- - Input SO implemented

-- 

-- Revision 1.2  2008/12/31 19:31:24  eda

-- Production Release

--  

-- 

--

-- VHDL Architecture r6502_tc.fsm_execution_unit.fsm

--

-- Created:

--          by - eda.UNKNOWN (ENTW-7HPZ200)

--          at - 22:31:13 15.09.2018

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)

--

-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt

-- 

-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.

-- 

-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.

-- 

-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.

-- 

-- 

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

architecture fsm of fsm_execution_unit is

   -- Architecture Declarations

   signal reg_F : std_logic_vector( 7 DOWNTO 0 );

   signal reg_sel_pc_in : std_logic;

   signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );

   signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );

   signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );

   signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );

   signal reg_sel_sp_as : std_logic;

   signal reg_sel_sp_in : std_logic;

   signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );

   signal sig_PC : std_logic_vector(15 DOWNTO 0);

   signal sig_RD : std_logic;

   signal sig_RWn : std_logic;

   signal sig_SYNC : std_logic;

   signal sig_WR : std_logic;

   signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );

   signal zw_alu : std_logic_vector(9 DOWNTO 0);

   signal zw_alu1 : std_logic_vector(9 DOWNTO 0);

   signal zw_alu2 : std_logic_vector(9 DOWNTO 0);

   signal zw_alu3 : std_logic_vector(9 DOWNTO 0);

   signal zw_alu4 : std_logic_vector(9 DOWNTO 0);

   signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_bit : std_logic;

   signal zw_irq : std_logic;

   signal zw_ninebits4 : std_logic_vector(8 DOWNTO 0);

   signal zw_nmi : std_logic;

   signal zw_so : std_logic;

   subtype state_type is

      std_logic_vector(7 downto 0);

   -- Hard encoding

   constant FETCH : state_type := "00000000";

   constant s0001 : state_type := "00000001";

   constant s0101 : state_type := "00000011";

   constant s0201 : state_type := "00000010";

   constant s0301 : state_type := "00000110";

   constant s0401 : state_type := "00000111";

   constant s1001 : state_type := "00000101";

   constant s1101 : state_type := "00000100";

   constant s1201 : state_type := "00001100";

   constant s1301 : state_type := "00001101";

   constant s1501 : state_type := "00001111";

   constant s1601 : state_type := "00001110";

   constant s1602 : state_type := "00001010";

   constant s1603 : state_type := "00001011";

   constant s1604 : state_type := "00001001";

   constant s2601 : state_type := "00001000";

   constant s2605 : state_type := "00011000";

   constant s2604 : state_type := "00011001";

   constant s2603 : state_type := "00011011";

   constant s2602 : state_type := "00011010";

   constant s2606 : state_type := "00011110";

   constant s2607 : state_type := "00011111";

   constant s2608 : state_type := "00011101";

   constant s2609 : state_type := "00011100";

   constant s2610 : state_type := "00010100";

   constant s2611 : state_type := "00010101";

   constant s1901 : state_type := "00010111";

   constant s1902 : state_type := "00010110";

   constant s2001 : state_type := "00010010";

   constant s2002 : state_type := "00010011";

   constant s2101 : state_type := "00010001";

   constant s2102 : state_type := "00010000";

   constant s2103 : state_type := "00110000";

   constant s2201 : state_type := "00110001";

   constant s2202 : state_type := "00110011";

   constant s2203 : state_type := "00110010";

   constant s2301 : state_type := "00110110";

   constant s2302 : state_type := "00110111";

   constant s2303 : state_type := "00110101";

   constant s2304 : state_type := "00110100";

   constant s2305 : state_type := "00111100";

   constant s2401 : state_type := "00111101";

   constant s2402 : state_type := "00111111";

   constant s2403 : state_type := "00111110";

   constant s2404 : state_type := "00111010";

   constant s2405 : state_type := "00111011";

   constant s1701 : state_type := "00111001";

   constant s1702 : state_type := "00111000";

   constant s1703 : state_type := "00101000";

   constant s1704 : state_type := "00101001";

   constant s1705 : state_type := "00101011";

   constant s0901 : state_type := "00101010";

   constant s0902 : state_type := "00101110";

   constant s0903 : state_type := "00101111";

   constant s9901 : state_type := "00101101";

   constant s9903 : state_type := "00101100";

   constant s9904 : state_type := "00100100";

   constant s9905 : state_type := "00100101";

   constant s9906 : state_type := "00100111";

   constant s9902 : state_type := "00100110";

   constant s2801 : state_type := "00100010";

   constant s2901 : state_type := "00100011";

   constant s3001 : state_type := "00100001";

   constant s3101 : state_type := "00100000";

   constant s1801 : state_type := "01100000";

   constant s1803 : state_type := "01100001";

   constant s1805 : state_type := "01100011";

   constant s1806 : state_type := "01100010";

   constant s1802 : state_type := "01100110";

   constant s1804 : state_type := "01100111";

   constant s1808 : state_type := "01100101";

   constant s1807 : state_type := "01100100";

   constant s1810 : state_type := "01101100";

   constant s1809 : state_type := "01101101";

   constant s1401 : state_type := "01101111";

   constant s1403 : state_type := "01101110";

   constant s1404 : state_type := "01101010";

   constant s1402 : state_type := "01101011";

   constant s1405 : state_type := "01101001";

   constant s1406 : state_type := "01101000";

   constant s1407 : state_type := "01111000";

   constant s1408 : state_type := "01111001";

   constant s0801 : state_type := "01111011";

   constant s0803 : state_type := "01111010";

   constant s0802 : state_type := "01111110";

   constant s0601 : state_type := "01111111";

   constant s0603 : state_type := "01111101";

   constant s0604 : state_type := "01111100";

   constant s0602 : state_type := "01110100";

   constant s0605 : state_type := "01110101";

   constant s0606 : state_type := "01110111";

   constant s0607 : state_type := "01110110";

   constant s0608 : state_type := "01110010";

   constant s0501 : state_type := "01110011";

   constant s0503 : state_type := "01110001";

   constant s0505 : state_type := "01110000";

   constant s0506 : state_type := "01010000";

   constant s0502 : state_type := "01010001";

   constant s0504 : state_type := "01010011";

   constant s0507 : state_type := "01010010";

   constant s0509 : state_type := "01010110";

   constant s0510 : state_type := "01010111";

   constant s0508 : state_type := "01010101";

   constant s0701 : state_type := "01010100";

   constant s0702 : state_type := "01011100";

   constant s0703 : state_type := "01011101";

   constant s2501 : state_type := "01011111";

   constant s2503 : state_type := "01011110";

   constant s2505 : state_type := "01011010";

   constant s2506 : state_type := "01011011";

   constant s2502 : state_type := "01011001";

   constant s2504 : state_type := "01011000";

   constant s2507 : state_type := "01001000";

   constant s2508 : state_type := "01001001";

   constant s2509 : state_type := "01001011";

   constant s2510 : state_type := "01001010";

   constant s2701 : state_type := "01001110";

   constant s2702 : state_type := "01001111";

   constant s2703 : state_type := "01001101";

   constant s2704 : state_type := "01001100";

   constant s2707 : state_type := "01000100";

   constant s2706 : state_type := "01000101";

   constant s2705 : state_type := "01000111";

   constant s0905 : state_type := "01000110";

   constant s0907 : state_type := "01000010";

   constant s0906 : state_type := "01000011";

   constant s0904 : state_type := "01000001";

   constant RES : state_type := "01000000";

   constant RES7 : state_type := "11000000";

   -- Declare current and next state signals

   signal current_state : state_type;

   signal next_state : state_type;

   -- Declare any pre-registered internal signals

   signal d_o_cld : std_logic_vector ( 7 downto 0 );

   signal rd_o_cld : std_logic ;

   signal sync_o_cld : std_logic ;

   signal wr_n_o_cld : std_logic ;

   signal wr_o_cld : std_logic ;

begin

   -----------------------------------------------------------------

   clocked_proc : process (

      clk_clk_i,

      rst_rst_n_i

   )

   -----------------------------------------------------------------

   begin

      if (rst_rst_n_i = '0') then

         current_state <= RES;

         -- Default Reset Values

         d_o_cld <= X"00";

         rd_o_cld <= '0';

         sync_o_cld <= '0';

         wr_n_o_cld <= '1';

         wr_o_cld <= '0';

         reg_F <= "00110100";

         reg_sel_pc_in <= '0';

         reg_sel_pc_val <= "00";

         reg_sel_rb_in <= "00";

         reg_sel_rb_out <= "00";

         reg_sel_reg <= "00";

         reg_sel_sp_as <= '0';

         reg_sel_sp_in <= '0';

         sig_PC <= X"0000";

         zw_REG_OP <= X"00";

         zw_b1 <= X"00";

         zw_b2 <= X"00";

         zw_b3 <= X"00";

         zw_b4 <= X"00";

         zw_bit <= '0';

         zw_irq <= '0';

         zw_nmi <= '0';

         zw_so <= '0';

      elsif (clk_clk_i'event and clk_clk_i = '1') then

         current_state <= next_state;

         -- Default Assignment To Internals

         reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);

         reg_sel_pc_in <= reg_sel_pc_in;

         reg_sel_pc_val <= reg_sel_pc_val;

         reg_sel_rb_in <= reg_sel_rb_in;

         reg_sel_rb_out <= reg_sel_rb_out;

         reg_sel_reg <= reg_sel_reg;

         reg_sel_sp_as <= reg_sel_sp_as;

         reg_sel_sp_in <= reg_sel_sp_in;

         sig_PC <= sig_PC;

         zw_REG_OP <= zw_REG_OP;

         zw_b1 <= zw_b1;

         zw_b2 <= zw_b2;

         zw_b3 <= zw_b3;

         zw_b4 <= zw_b4;

         zw_bit <= zw_bit;

         zw_irq <= zw_irq;

         zw_nmi <= zw_nmi;

         zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));

         d_o_cld <= sig_D_OUT;

         rd_o_cld <= sig_RD;

         sync_o_cld <= sig_SYNC;

         wr_n_o_cld <= sig_RWn;

         wr_o_cld <= sig_WR;

         -- Combined Actions

         case current_state is

            when FETCH =>

               zw_REG_OP <= d_i;

               if ((d_i = X"00") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((nmi_i = '1') and (rdy_i = '1')) then

                  reg_sel_pc_in <= '0';

                  reg_sel_pc_val <= "00";

                  reg_sel_sp_in <= '0';

                  reg_sel_sp_as <= '1';

                  zw_nmi <= '0';

               elsif ((irq_n_i = '0' and

                      reg_F(2) = '0') and (rdy_i = '1')) then

                  reg_sel_pc_in <= '0';

                  reg_sel_pc_val <= "00";

                  reg_sel_sp_in <= '0';

                  reg_sel_sp_as <= '1';

                  zw_irq <= '0';

               elsif ((d_i = X"69" or

                      d_i = X"65" or

                      d_i = X"75" or

                      d_i = X"6D" or

                      d_i = X"7D" or

                      d_i = X"79" or

                      d_i = X"61" or

                      d_i = X"71") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

                  reg_sel_reg <= "00";

                  reg_sel_rb_in <= "11";

               elsif ((d_i = X"06" or

                      d_i = X"16" or

                      d_i = X"0E" or

                      d_i = X"1E") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"90" or

                      d_i = X"B0" or

                      d_i = X"F0" or

                      d_i = X"30" or

                      d_i = X"D0" or

                      d_i = X"10" or

                      d_i = X"50" or

                      d_i = X"70") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"24" or

                      d_i = X"2C") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"18") and (rdy_i = '1')) then

               elsif ((d_i = X"D8") and (rdy_i = '1')) then

               elsif ((d_i = X"58") and (rdy_i = '1')) then

                  reg_F(2) <= '0';

               elsif ((d_i = X"B8") and (rdy_i = '1')) then

               elsif ((d_i = X"E0" or

                      d_i = X"E4" or

                      d_i = X"EC") and (rdy_i = '1')) then

                  reg_sel_rb_out <= "01";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"C0" or

                      d_i = X"C4" or

                      d_i = X"CC") and (rdy_i = '1')) then

                  reg_sel_rb_out <= "10";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"C6" or

                      d_i = X"D6" or

                      d_i = X"CE" or

                      d_i = X"DE") and (rdy_i = '1')) then

                  zw_b4 <= X"FF";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"CA") and (rdy_i = '1')) then

                  reg_sel_rb_out <= "01";

                  reg_sel_reg <= "01";

                  reg_sel_rb_in <= "11";

                  zw_b4 <= X"FF";

               elsif ((d_i = X"88") and (rdy_i = '1')) then

                  reg_sel_rb_out <= "10";

                  reg_sel_reg <= "10";

                  reg_sel_rb_in <= "11";

                  zw_b4 <= X"FF";

               elsif ((d_i = X"49" or

                      d_i = X"45" or

                      d_i = X"55" or

                      d_i = X"4D" or

                      d_i = X"5D" or

                      d_i = X"59" or

                      d_i = X"41" or

                      d_i = X"51" or

                      d_i = X"09" or

                      d_i = X"05" or

                      d_i = X"15" or

                      d_i = X"0D" or

                      d_i = X"1D" or

                      d_i = X"19" or

                      d_i = X"01" or

                      d_i = X"11" or

                      d_i = X"29" or

                      d_i = X"25" or

                      d_i = X"35" or

                      d_i = X"2D" or

                      d_i = X"3D" or

                      d_i = X"39" or

                      d_i = X"21" or

                      d_i = X"31" or

                      d_i = X"C9" or

                      d_i = X"C5" or

                      d_i = X"D5" or

                      d_i = X"CD" or

                      d_i = X"DD" or

                      d_i = X"D9" or

                      d_i = X"C1" or

                      d_i = X"D1") and (rdy_i = '1')) then

                  reg_sel_rb_out <= "00";

                  reg_sel_reg <= "00";

                  reg_sel_rb_in <= "11";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"E6" or

                      d_i = X"F6" or

                      d_i = X"EE" or

                      d_i = X"FE") and (rdy_i = '1')) then

                  zw_b4 <= X"01";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"E8") and (rdy_i = '1')) then

                  reg_sel_rb_out <= "01";

                  reg_sel_reg <= "01";

                  reg_sel_rb_in <= "11";

                  zw_b4 <= X"01";

               elsif ((d_i = X"C8") and (rdy_i = '1')) then

                  reg_sel_rb_out <= "10";

                  reg_sel_reg <= "10";

                  reg_sel_rb_in <= "11";

                  zw_b4 <= X"01";

               elsif ((d_i = X"4C" or

                      d_i = X"6C") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"20") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"A9" or

                      d_i = X"A5" or

                      d_i = X"B5" or

                      d_i = X"AD" or

                      d_i = X"BD" or

                      d_i = X"B9" or

                      d_i = X"A1" or

                      d_i = X"B1") and (rdy_i = '1')) then

                  reg_sel_reg <= "00";

                  reg_sel_rb_in <= "11";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"A2" or

                      d_i = X"A6" or

                      d_i = X"B6" or

                      d_i = X"AE" or

                      d_i = X"BE") and (rdy_i = '1')) then

                  reg_sel_reg <= "01";

                  reg_sel_rb_in <= "11";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"A0" or

                      d_i = X"A4" or

                      d_i = X"B4" or

                      d_i = X"AC" or

                      d_i = X"BC") and (rdy_i = '1')) then

                  reg_sel_reg <= "10";

                  reg_sel_rb_in <= "11";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"46" or

                      d_i = X"56" or

                      d_i = X"4E" or

                      d_i = X"5E") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"EA") and (rdy_i = '1')) then

               elsif ((d_i = X"48") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"08") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"68") and (rdy_i = '1')) then

                  reg_sel_sp_in <= '0';

                  reg_sel_sp_as <= '0';

                  reg_sel_reg <= "00";

                  reg_sel_rb_in <= "11";

               elsif ((d_i = X"28") and (rdy_i = '1')) then

                  reg_sel_sp_in <= '0';

                  reg_sel_sp_as <= '0';

               elsif ((d_i = X"26" or

                      d_i = X"36" or

                      d_i = X"2E" or

                      d_i = X"3E") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"66" or

                      d_i = X"76" or

                      d_i = X"6E" or

                      d_i = X"7E") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"40") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;