| 1 |
24 |
fpga_is_fu |
(January 31th 2020)
|
| 2 |
|
|
- (PLANED) Transfer the new two branches v1.53 (BASE) and v2.00 (HIGH SPEED) to meaningful core names.
|
| 3 |
|
|
-> avoiding confusions between current version numbering (root is cpu65c02_tc v1.52) and
|
| 4 |
|
|
variants like "BASE" and "HIGH SPEED" (future names maybe different).
|
| 5 |
|
|
- (DONE) Creating test strategy for RDY signal
|
| 6 |
|
|
|
| 7 |
23 |
fpga_is_fu |
(October 15th 2018)
|
| 8 |
24 |
fpga_is_fu |
- (DONE) Add seperated area for BETA and RELEASE CANDIDATES
|
| 9 |
|
|
- (DONE) Performance improvements
|
| 10 |
|
|
- (WORKING) Creating test strategy for RDY signal
|
| 11 |
23 |
fpga_is_fu |
- (DONE) Finish working for Specification of cpu65C02_tc
|
| 12 |
24 |
fpga_is_fu |
|
| 13 |
20 |
fpga_is_fu |
(September 09th 2018)
|
| 14 |
24 |
fpga_is_fu |
- (WORKING) Performance improvements
|
| 15 |
|
|
- (WORKING) Creating test strategy for RDY signal
|
| 16 |
|
|
- (DONE) Working on reported Bugs/Requests: JMP, Branches, Interrupts, ADC/SBC
|
| 17 |
|
|
- (DONE) Verifying all interrupts
|
| 18 |
20 |
fpga_is_fu |
- (90%) Finish working for Specification of cpu65C02_tc
|
| 19 |
24 |
fpga_is_fu |
|
| 20 |
18 |
fpga_is_fu |
(July 31th 2013)
|
| 21 |
|
|
- (DONE) Transfer the project state from "BETA" to "RELEASE CANDIDATE"
|
| 22 |
|
|
- (DONE) Offer a high level testbench in assembler for testing all Op Codes
|
| 23 |
|
|
Including Klaus Dormann's "65c02_*_test" suite
|
| 24 |
|
|
- (DONE) Because of translation errors the Verilog sources are no longer
|
| 25 |
|
|
available
|
| 26 |
|
|
- (DONE) Create "golden" simulation files for Modelsim/QuestaSim
|
| 27 |
|
|
- (75%) Finish working for Specification of cpu65C02_tc
|
| 28 |
|
|
- (85%) Finish working for Specification of cpu65C02_tc
|
| 29 |
|
|
|
| 30 |
|
|
|
| 31 |
12 |
fpga_is_fu |
(February 25th 2009)
|
| 32 |
|
|
- (DONE) CORRECTED "RTI" (wrong: use of stack pointer)
|
| 33 |
|
|
- (DONE) CORRECTED "RMBx" & "SMBx" (wrong: bit translation)
|
| 34 |
|
|
- (DONE) RENAME all states of "FSM Execution Unit" for better reading
|
| 35 |
|
|
- (85%) Finish working for Specification of cpu65C02_tc
|
| 36 |
18 |
fpga_is_fu |
- (DONE) CORRECT timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles
|
| 37 |
|
|
instead of 7)
|
| 38 |
12 |
fpga_is_fu |
- (DONE) OPTIMIZE end states of "STA" (s197,s207,s200,s213)
|
| 39 |
|
|
|
| 40 |
7 |
fpga_is_fu |
(January, 4th 2009)
|
| 41 |
|
|
- (DONE) Remove unused nets, register and modules
|
| 42 |
|
|
- (DONE) Update the HDL Designer files for better viewing and
|
| 43 |
|
|
understanding
|
| 44 |
|
|
|
| 45 |
2 |
fpga_is_fu |
(August, 5th 2008)
|
| 46 |
4 |
fpga_is_fu |
- (DONE) Rename all port names (_i, _o, _o_i)
|
| 47 |
|
|
- (DONE) Test and verify all Op Codes
|
| 48 |
|
|
- (DONE) Optimize core for speed
|
| 49 |
|
|
- (DONE) Implement same improvements like cpu6502_tc (graphical design, source
|
| 50 |
2 |
fpga_is_fu |
utilisation...)
|
| 51 |
4 |
fpga_is_fu |
- (75%) Finish working for Specification of cpu65C02_tc
|
| 52 |
7 |
fpga_is_fu |
- (WORKING) Create high level testbench in assembler and hardware for
|
| 53 |
2 |
fpga_is_fu |
testing all Op Codes (include accurate cycle timing)
|
| 54 |
7 |
fpga_is_fu |
- (WORKING) Create simulation files for Modelsim
|
| 55 |
|
|
- (WORKING) Create a simple .wlf file to demonstrate the cpu65C02_tc
|
| 56 |
2 |
fpga_is_fu |
- Update the HDL Designer files for better viewing and understanding
|
