1 |
24 |
fpga_is_fu |
LIBRARY ieee;
|
2 |
|
|
USE ieee.std_logic_1164.all;
|
3 |
|
|
USE ieee.std_logic_arith.all;
|
4 |
|
|
|
5 |
|
|
entity core is
|
6 |
|
|
port(
|
7 |
|
|
clk_clk_i : in std_logic;
|
8 |
|
|
d_i : in std_logic_vector (7 downto 0);
|
9 |
|
|
irq_n_i : in std_logic;
|
10 |
|
|
nmi_n_i : in std_logic;
|
11 |
|
|
rdy_i : in std_logic;
|
12 |
|
|
rst_rst_n_i : in std_logic;
|
13 |
|
|
so_n_i : in std_logic;
|
14 |
|
|
a_o : out std_logic_vector (15 downto 0);
|
15 |
|
|
d_o : out std_logic_vector (7 downto 0);
|
16 |
|
|
rd_o : out std_logic;
|
17 |
|
|
sync_o : out std_logic;
|
18 |
|
|
wr_n_o : out std_logic;
|
19 |
|
|
wr_o : out std_logic
|
20 |
|
|
);
|
21 |
|
|
|
22 |
|
|
-- Declarations
|
23 |
|
|
|
24 |
|
|
end core ;
|
25 |
|
|
-- (C) 2008 - 2021 Jens Gutschmidt
|
26 |
|
|
-- (email: opencores@vivare-services.com)
|
27 |
|
|
--
|
28 |
|
|
-- Versions:
|
29 |
|
|
-- Revision 1.8 2013/08/01 11:00:00 jens
|
30 |
|
|
-- - Change Block names to lower case
|
31 |
|
|
-- - Bug Fix RMB, SMB Bug - Bit position decoded wrong. Adding a priority encoder.
|
32 |
|
|
--
|
33 |
|
|
-- Revision 1.7 2013/07/21 11:11:00 jens
|
34 |
|
|
-- - Changing the title block and internal revision history
|
35 |
|
|
--
|
36 |
|
|
-- Revision 1.6 2009/01/04 10:20:47 eda
|
37 |
|
|
-- Changes for cosmetic issues only
|
38 |
|
|
--
|
39 |
|
|
-- Revision 1.5 2009/01/04 09:23:10 eda
|
40 |
|
|
-- - Delete unused nets and blocks (same as R6502_TC)
|
41 |
|
|
-- - Rename blocks
|
42 |
|
|
--
|
43 |
|
|
-- Revision 1.4 2009/01/03 16:53:02 eda
|
44 |
|
|
-- - Unused nets and blocks deleted
|
45 |
|
|
-- - Renamed blocks
|
46 |
|
|
--
|
47 |
|
|
-- Revision 1.3 2009/01/03 16:42:02 eda
|
48 |
|
|
-- - Unused nets and blocks deleted
|
49 |
|
|
-- - Renamed blocks
|
50 |
|
|
--
|
51 |
|
|
-- Revision 1.2 2008/12/31 19:31:24 eda
|
52 |
|
|
-- Production Release
|
53 |
|
|
--
|
54 |
|
|
--
|
55 |
|
|
--
|
56 |
|
|
-- r65c02_tc.core.struct
|
57 |
|
|
--
|
58 |
|
|
-- Date: 09.01.2021
|
59 |
|
|
-- Time: 16:59:58
|
60 |
|
|
-- By: VIVARE GmbH, Switzerland
|
61 |
|
|
--
|
62 |
|
|
-- COPYRIGHT (C) 2008 - 2021 by Jens Gutschmidt
|
63 |
|
|
--
|
64 |
|
|
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
|
65 |
|
|
--
|
66 |
|
|
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
67 |
|
|
--
|
68 |
|
|
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
|
69 |
|
|
--
|
70 |
|
|
--
|
71 |
|
|
LIBRARY ieee;
|
72 |
|
|
USE ieee.std_logic_1164.all;
|
73 |
|
|
USE ieee.std_logic_arith.all;
|
74 |
|
|
|
75 |
|
|
library r65c02_tc;
|
76 |
|
|
|
77 |
|
|
architecture struct of core is
|
78 |
|
|
|
79 |
|
|
-- Architecture declarations
|
80 |
|
|
|
81 |
|
|
-- Internal signal declarations
|
82 |
|
|
signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);
|
83 |
|
|
signal adr_o_i : std_logic_vector(15 downto 0);
|
84 |
|
|
signal adr_pc_o_i : std_logic_vector(15 downto 0);
|
85 |
|
|
signal adr_sp_o_i : std_logic_vector(15 downto 0);
|
86 |
|
|
signal ch_a_o_i : std_logic_vector(7 downto 0);
|
87 |
|
|
signal ch_b_o_i : std_logic_vector(7 downto 0);
|
88 |
|
|
signal d_alu_n_o_i : std_logic;
|
89 |
|
|
signal d_alu_o_i : std_logic_vector(7 downto 0);
|
90 |
|
|
signal d_alu_or_o_i : std_logic;
|
91 |
|
|
signal d_alu_prio_o_i : std_logic_vector(7 downto 0);
|
92 |
|
|
signal d_regs_in_o_i : std_logic_vector(7 downto 0);
|
93 |
|
|
signal d_regs_out_o_i : std_logic_vector(7 downto 0);
|
94 |
|
|
signal ld_o_i : std_logic_vector(1 downto 0);
|
95 |
|
|
signal ld_pc_o_i : std_logic;
|
96 |
|
|
signal ld_sp_o_i : std_logic;
|
97 |
|
|
signal load_regs_o_i : std_logic;
|
98 |
|
|
signal nmi_o_i : std_logic;
|
99 |
|
|
signal offset_o_i : std_logic_vector(15 downto 0);
|
100 |
|
|
signal q_a_o_i : std_logic_vector(7 downto 0);
|
101 |
|
|
signal q_x_o_i : std_logic_vector(7 downto 0);
|
102 |
|
|
signal q_y_o_i : std_logic_vector(7 downto 0);
|
103 |
|
|
signal reg_0flag_o_i : std_logic;
|
104 |
|
|
signal reg_1flag_o_i : std_logic;
|
105 |
|
|
signal reg_7flag_o_i : std_logic;
|
106 |
|
|
signal rst_nmi_o_i : std_logic;
|
107 |
|
|
signal sel_pc_in_o_i : std_logic;
|
108 |
|
|
signal sel_pc_val_o_i : std_logic_vector(1 downto 0);
|
109 |
|
|
signal sel_rb_in_o_i : std_logic_vector(1 downto 0);
|
110 |
|
|
signal sel_rb_out_o_i : std_logic_vector(1 downto 0);
|
111 |
|
|
signal sel_reg_o_i : std_logic_vector(1 downto 0);
|
112 |
|
|
signal sel_sp_as_o_i : std_logic;
|
113 |
|
|
signal sel_sp_in_o_i : std_logic;
|
114 |
|
|
signal var_shift_data_o_i : std_logic_vector(7 downto 0);
|
115 |
|
|
|
116 |
|
|
|
117 |
|
|
-- Component Declarations
|
118 |
|
|
component fsm_execution_unit
|
119 |
|
|
port (
|
120 |
|
|
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
|
121 |
|
|
adr_pc_i : in std_logic_vector (15 downto 0);
|
122 |
|
|
adr_sp_i : in std_logic_vector (15 downto 0);
|
123 |
|
|
clk_clk_i : in std_logic ;
|
124 |
|
|
d_alu_i : in std_logic_vector ( 7 downto 0 );
|
125 |
|
|
d_alu_prio_i : in std_logic_vector (7 downto 0);
|
126 |
|
|
d_i : in std_logic_vector ( 7 downto 0 );
|
127 |
|
|
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
|
128 |
|
|
irq_n_i : in std_logic ;
|
129 |
|
|
nmi_i : in std_logic ;
|
130 |
|
|
q_a_i : in std_logic_vector ( 7 downto 0 );
|
131 |
|
|
q_x_i : in std_logic_vector ( 7 downto 0 );
|
132 |
|
|
q_y_i : in std_logic_vector ( 7 downto 0 );
|
133 |
|
|
rdy_i : in std_logic ;
|
134 |
|
|
reg_0flag_i : in std_logic ;
|
135 |
|
|
reg_1flag_i : in std_logic ;
|
136 |
|
|
reg_7flag_i : in std_logic ;
|
137 |
|
|
rst_rst_n_i : in std_logic ;
|
138 |
|
|
so_n_i : in std_logic ;
|
139 |
|
|
a_o : out std_logic_vector (15 downto 0);
|
140 |
|
|
adr_o : out std_logic_vector (15 downto 0);
|
141 |
|
|
ch_a_o : out std_logic_vector ( 7 downto 0 );
|
142 |
|
|
ch_b_o : out std_logic_vector ( 7 downto 0 );
|
143 |
|
|
d_o : out std_logic_vector ( 7 downto 0 );
|
144 |
|
|
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
|
145 |
|
|
ld_o : out std_logic_vector ( 1 downto 0 );
|
146 |
|
|
ld_pc_o : out std_logic ;
|
147 |
|
|
ld_sp_o : out std_logic ;
|
148 |
|
|
load_regs_o : out std_logic ;
|
149 |
|
|
offset_o : out std_logic_vector ( 15 downto 0 );
|
150 |
|
|
rd_o : out std_logic ;
|
151 |
|
|
rst_nmi_o : out std_logic ;
|
152 |
|
|
sel_pc_in_o : out std_logic ;
|
153 |
|
|
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
|
154 |
|
|
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
|
155 |
|
|
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
|
156 |
|
|
sel_reg_o : out std_logic_vector ( 1 downto 0 );
|
157 |
|
|
sel_sp_as_o : out std_logic ;
|
158 |
|
|
sel_sp_in_o : out std_logic ;
|
159 |
|
|
sync_o : out std_logic ;
|
160 |
|
|
wr_n_o : out std_logic ;
|
161 |
|
|
wr_o : out std_logic
|
162 |
|
|
);
|
163 |
|
|
end component;
|
164 |
|
|
component fsm_intnmi
|
165 |
|
|
port (
|
166 |
|
|
clk_clk_i : in std_logic ;
|
167 |
|
|
nmi_n_i : in std_logic ;
|
168 |
|
|
rst_nmi_i : in std_logic ;
|
169 |
|
|
rst_rst_n_i : in std_logic ;
|
170 |
|
|
nmi_o : out std_logic
|
171 |
|
|
);
|
172 |
|
|
end component;
|
173 |
|
|
component reg_pc
|
174 |
|
|
port (
|
175 |
|
|
adr_i : in std_logic_vector (15 downto 0);
|
176 |
|
|
clk_clk_i : in std_logic ;
|
177 |
|
|
ld_i : in std_logic_vector (1 downto 0);
|
178 |
|
|
ld_pc_i : in std_logic ;
|
179 |
|
|
offset_i : in std_logic_vector (15 downto 0);
|
180 |
|
|
rst_rst_n_i : in std_logic ;
|
181 |
|
|
sel_pc_in_i : in std_logic ;
|
182 |
|
|
sel_pc_val_i : in std_logic_vector (1 downto 0);
|
183 |
|
|
adr_nxt_pc_o : out std_logic_vector (15 downto 0);
|
184 |
|
|
adr_pc_o : out std_logic_vector (15 downto 0)
|
185 |
|
|
);
|
186 |
|
|
end component;
|
187 |
|
|
component reg_sp
|
188 |
|
|
port (
|
189 |
|
|
adr_low_i : in std_logic_vector (7 downto 0);
|
190 |
|
|
clk_clk_i : in std_logic ;
|
191 |
|
|
ld_low_i : in std_logic ;
|
192 |
|
|
ld_sp_i : in std_logic ;
|
193 |
|
|
rst_rst_n_i : in std_logic ;
|
194 |
|
|
sel_sp_as_i : in std_logic ;
|
195 |
|
|
sel_sp_in_i : in std_logic ;
|
196 |
|
|
adr_sp_o : out std_logic_vector (15 downto 0)
|
197 |
|
|
);
|
198 |
|
|
end component;
|
199 |
|
|
component regbank_axy
|
200 |
|
|
port (
|
201 |
|
|
clk_clk_i : in std_logic ;
|
202 |
|
|
d_regs_in_i : in std_logic_vector (7 downto 0);
|
203 |
|
|
load_regs_i : in std_logic ;
|
204 |
|
|
rst_rst_n_i : in std_logic ;
|
205 |
|
|
sel_rb_in_i : in std_logic_vector (1 downto 0);
|
206 |
|
|
sel_rb_out_i : in std_logic_vector (1 downto 0);
|
207 |
|
|
sel_reg_i : in std_logic_vector (1 downto 0);
|
208 |
|
|
d_regs_out_o : out std_logic_vector (7 downto 0);
|
209 |
|
|
q_a_o : out std_logic_vector (7 downto 0);
|
210 |
|
|
q_x_o : out std_logic_vector (7 downto 0);
|
211 |
|
|
q_y_o : out std_logic_vector (7 downto 0)
|
212 |
|
|
);
|
213 |
|
|
end component;
|
214 |
|
|
|
215 |
|
|
-- Optional embedded configurations
|
216 |
|
|
-- pragma synthesis_off
|
217 |
|
|
for all : fsm_execution_unit use entity r65c02_tc.fsm_execution_unit;
|
218 |
|
|
for all : fsm_intnmi use entity r65c02_tc.fsm_intnmi;
|
219 |
|
|
for all : reg_pc use entity r65c02_tc.reg_pc;
|
220 |
|
|
for all : reg_sp use entity r65c02_tc.reg_sp;
|
221 |
|
|
for all : regbank_axy use entity r65c02_tc.regbank_axy;
|
222 |
|
|
-- pragma synthesis_on
|
223 |
|
|
|
224 |
|
|
|
225 |
|
|
begin
|
226 |
|
|
-- Architecture concurrent statements
|
227 |
|
|
-- HDL Embedded Text Block 1 eb1
|
228 |
|
|
-- eb1 1
|
229 |
|
|
var_shift_data_o_i <= x"01";
|
230 |
|
|
|
231 |
|
|
|
232 |
|
|
-- ModuleWare code(v1.12) for instance 'U_11' of 'add'
|
233 |
|
|
u_11combo_proc: process (ch_a_o_i, ch_b_o_i)
|
234 |
|
|
variable temp_din0 : std_logic_vector(8 downto 0);
|
235 |
|
|
variable temp_din1 : std_logic_vector(8 downto 0);
|
236 |
|
|
variable temp_sum : unsigned(8 downto 0);
|
237 |
|
|
variable temp_carry : std_logic;
|
238 |
|
|
begin
|
239 |
|
|
temp_din0 := '0' & ch_a_o_i;
|
240 |
|
|
temp_din1 := '0' & ch_b_o_i;
|
241 |
|
|
temp_carry := '0';
|
242 |
|
|
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
|
243 |
|
|
d_alu_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8);
|
244 |
|
|
reg_0flag_o_i <= temp_sum(8) ;
|
245 |
|
|
end process u_11combo_proc;
|
246 |
|
|
|
247 |
|
|
-- ModuleWare code(v1.12) for instance 'U_8' of 'inv'
|
248 |
|
|
reg_1flag_o_i <= not(d_alu_or_o_i);
|
249 |
|
|
|
250 |
|
|
-- ModuleWare code(v1.12) for instance 'U_9' of 'inv'
|
251 |
|
|
reg_7flag_o_i <= not(d_alu_n_o_i);
|
252 |
|
|
|
253 |
|
|
-- ModuleWare code(v1.12) for instance 'U_10' of 'inv'
|
254 |
|
|
d_alu_n_o_i <= not(d_alu_o_i(7));
|
255 |
|
|
|
256 |
|
|
-- ModuleWare code(v1.12) for instance 'U_5' of 'lshift'
|
257 |
|
|
u_5combo_proc : process (var_shift_data_o_i, ch_a_o_i)
|
258 |
|
|
variable temp_shift : std_logic_vector (3 downto 0);
|
259 |
|
|
variable temp_dout : std_logic_vector (7 downto 0);
|
260 |
|
|
variable temp_din : std_logic_vector (7 downto 0);
|
261 |
|
|
begin
|
262 |
|
|
temp_din := (others=> 'X');
|
263 |
|
|
temp_shift := ch_a_o_i(3 downto 0);
|
264 |
|
|
temp_din := var_shift_data_o_i;
|
265 |
|
|
for i in 0 to 3 loop
|
266 |
|
|
if (i < 3) then
|
267 |
|
|
if (temp_shift(i) = '1') then
|
268 |
|
|
temp_dout := (others => '0');
|
269 |
|
|
temp_dout(7 downto 2**i) := temp_din(7 - 2**i downto 0);
|
270 |
|
|
elsif (temp_shift(i) = '0') then
|
271 |
|
|
temp_dout := temp_din;
|
272 |
|
|
else
|
273 |
|
|
temp_dout := (others => 'X');
|
274 |
|
|
end if;
|
275 |
|
|
else
|
276 |
|
|
if (temp_shift(i) = '1') then
|
277 |
|
|
temp_dout := (others => '0');
|
278 |
|
|
elsif (temp_shift(i) = '0') then
|
279 |
|
|
temp_dout := temp_din;
|
280 |
|
|
else
|
281 |
|
|
temp_dout := (others => 'X');
|
282 |
|
|
end if;
|
283 |
|
|
end if;
|
284 |
|
|
temp_din := temp_dout;
|
285 |
|
|
end loop;
|
286 |
|
|
d_alu_prio_o_i <= temp_dout;
|
287 |
|
|
end process u_5combo_proc;
|
288 |
|
|
|
289 |
|
|
-- ModuleWare code(v1.12) for instance 'U_7' of 'por'
|
290 |
|
|
d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7);
|
291 |
|
|
|
292 |
|
|
-- Instance port mappings.
|
293 |
|
|
U_4 : fsm_execution_unit
|
294 |
|
|
port map (
|
295 |
|
|
adr_nxt_pc_i => adr_nxt_pc_o_i,
|
296 |
|
|
adr_pc_i => adr_pc_o_i,
|
297 |
|
|
adr_sp_i => adr_sp_o_i,
|
298 |
|
|
clk_clk_i => clk_clk_i,
|
299 |
|
|
d_alu_i => d_alu_o_i,
|
300 |
|
|
d_alu_prio_i => d_alu_prio_o_i,
|
301 |
|
|
d_i => d_i,
|
302 |
|
|
d_regs_out_i => d_regs_out_o_i,
|
303 |
|
|
irq_n_i => irq_n_i,
|
304 |
|
|
nmi_i => nmi_o_i,
|
305 |
|
|
q_a_i => q_a_o_i,
|
306 |
|
|
q_x_i => q_x_o_i,
|
307 |
|
|
q_y_i => q_y_o_i,
|
308 |
|
|
rdy_i => rdy_i,
|
309 |
|
|
reg_0flag_i => reg_0flag_o_i,
|
310 |
|
|
reg_1flag_i => reg_1flag_o_i,
|
311 |
|
|
reg_7flag_i => reg_7flag_o_i,
|
312 |
|
|
rst_rst_n_i => rst_rst_n_i,
|
313 |
|
|
so_n_i => so_n_i,
|
314 |
|
|
a_o => a_o,
|
315 |
|
|
adr_o => adr_o_i,
|
316 |
|
|
ch_a_o => ch_a_o_i,
|
317 |
|
|
ch_b_o => ch_b_o_i,
|
318 |
|
|
d_o => d_o,
|
319 |
|
|
d_regs_in_o => d_regs_in_o_i,
|
320 |
|
|
ld_o => ld_o_i,
|
321 |
|
|
ld_pc_o => ld_pc_o_i,
|
322 |
|
|
ld_sp_o => ld_sp_o_i,
|
323 |
|
|
load_regs_o => load_regs_o_i,
|
324 |
|
|
offset_o => offset_o_i,
|
325 |
|
|
rd_o => rd_o,
|
326 |
|
|
rst_nmi_o => rst_nmi_o_i,
|
327 |
|
|
sel_pc_in_o => sel_pc_in_o_i,
|
328 |
|
|
sel_pc_val_o => sel_pc_val_o_i,
|
329 |
|
|
sel_rb_in_o => sel_rb_in_o_i,
|
330 |
|
|
sel_rb_out_o => sel_rb_out_o_i,
|
331 |
|
|
sel_reg_o => sel_reg_o_i,
|
332 |
|
|
sel_sp_as_o => sel_sp_as_o_i,
|
333 |
|
|
sel_sp_in_o => sel_sp_in_o_i,
|
334 |
|
|
sync_o => sync_o,
|
335 |
|
|
wr_n_o => wr_n_o,
|
336 |
|
|
wr_o => wr_o
|
337 |
|
|
);
|
338 |
|
|
U_3 : fsm_intnmi
|
339 |
|
|
port map (
|
340 |
|
|
clk_clk_i => clk_clk_i,
|
341 |
|
|
nmi_n_i => nmi_n_i,
|
342 |
|
|
rst_nmi_i => rst_nmi_o_i,
|
343 |
|
|
rst_rst_n_i => rst_rst_n_i,
|
344 |
|
|
nmi_o => nmi_o_i
|
345 |
|
|
);
|
346 |
|
|
U_0 : reg_pc
|
347 |
|
|
port map (
|
348 |
|
|
adr_i => adr_o_i,
|
349 |
|
|
clk_clk_i => clk_clk_i,
|
350 |
|
|
ld_i => ld_o_i,
|
351 |
|
|
ld_pc_i => ld_pc_o_i,
|
352 |
|
|
offset_i => offset_o_i,
|
353 |
|
|
rst_rst_n_i => rst_rst_n_i,
|
354 |
|
|
sel_pc_in_i => sel_pc_in_o_i,
|
355 |
|
|
sel_pc_val_i => sel_pc_val_o_i,
|
356 |
|
|
adr_nxt_pc_o => adr_nxt_pc_o_i,
|
357 |
|
|
adr_pc_o => adr_pc_o_i
|
358 |
|
|
);
|
359 |
|
|
U_1 : reg_sp
|
360 |
|
|
port map (
|
361 |
|
|
adr_low_i => adr_o_i(7 DOWNTO 0),
|
362 |
|
|
clk_clk_i => clk_clk_i,
|
363 |
|
|
ld_low_i => ld_o_i(0),
|
364 |
|
|
ld_sp_i => ld_sp_o_i,
|
365 |
|
|
rst_rst_n_i => rst_rst_n_i,
|
366 |
|
|
sel_sp_as_i => sel_sp_as_o_i,
|
367 |
|
|
sel_sp_in_i => sel_sp_in_o_i,
|
368 |
|
|
adr_sp_o => adr_sp_o_i
|
369 |
|
|
);
|
370 |
|
|
U_2 : regbank_axy
|
371 |
|
|
port map (
|
372 |
|
|
clk_clk_i => clk_clk_i,
|
373 |
|
|
d_regs_in_i => d_regs_in_o_i,
|
374 |
|
|
load_regs_i => load_regs_o_i,
|
375 |
|
|
rst_rst_n_i => rst_rst_n_i,
|
376 |
|
|
sel_rb_in_i => sel_rb_in_o_i,
|
377 |
|
|
sel_rb_out_i => sel_rb_out_o_i,
|
378 |
|
|
sel_reg_i => sel_reg_o_i,
|
379 |
|
|
d_regs_out_o => d_regs_out_o_i,
|
380 |
|
|
q_a_o => q_a_o_i,
|
381 |
|
|
q_x_o => q_x_o_i,
|
382 |
|
|
q_y_o => q_y_o_i
|
383 |
|
|
);
|
384 |
|
|
|
385 |
|
|
end struct;
|