Subversion Repositories cpu65c02_true_cycle

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

entity fsm_execution_unit is

   port(

      adr_nxt_pc_i : in     std_logic_vector (15 downto 0);

      adr_pc_i     : in     std_logic_vector (15 downto 0);

      adr_sp_i     : in     std_logic_vector (15 downto 0);

      clk_clk_i    : in     std_logic;

      d_alu_i      : in     std_logic_vector ( 7 downto 0 );

      d_alu_prio_i : in     std_logic_vector (7 downto 0);

      d_i          : in     std_logic_vector ( 7 downto 0 );

      d_regs_out_i : in     std_logic_vector ( 7 downto 0 );

      irq_n_i      : in     std_logic;

      nmi_i        : in     std_logic;

      q_a_i        : in     std_logic_vector ( 7 downto 0 );

      q_x_i        : in     std_logic_vector ( 7 downto 0 );

      q_y_i        : in     std_logic_vector ( 7 downto 0 );

      rdy_i        : in     std_logic;

      reg_0flag_i  : in     std_logic;

      reg_1flag_i  : in     std_logic;

      reg_7flag_i  : in     std_logic;

      rst_rst_n_i  : in     std_logic;

      so_n_i       : in     std_logic;

      a_o          : out    std_logic_vector (15 downto 0);

      adr_o        : out    std_logic_vector (15 downto 0);

      ch_a_o       : out    std_logic_vector ( 7 downto 0 );

      ch_b_o       : out    std_logic_vector ( 7 downto 0 );

      d_o          : out    std_logic_vector ( 7 downto 0 );

      d_regs_in_o  : out    std_logic_vector ( 7 downto 0 );

      ld_o         : out    std_logic_vector ( 1 downto 0 );

      ld_pc_o      : out    std_logic;

      ld_sp_o      : out    std_logic;

      load_regs_o  : out    std_logic;

      offset_o     : out    std_logic_vector ( 15 downto 0 );

      rd_o         : out    std_logic;

      rst_nmi_o    : out    std_logic;

      sel_pc_in_o  : out    std_logic;

      sel_pc_val_o : out    std_logic_vector ( 1 downto 0 );

      sel_rb_in_o  : out    std_logic_vector ( 1 downto 0 );

      sel_rb_out_o : out    std_logic_vector ( 1 downto 0 );

      sel_reg_o    : out    std_logic_vector ( 1 downto 0 );

      sel_sp_as_o  : out    std_logic;

      sel_sp_in_o  : out    std_logic;

      sync_o       : out    std_logic;

      wr_n_o       : out    std_logic;

      wr_o         : out    std_logic

   );

-- Declarations

end fsm_execution_unit ;

-- (C) 2008 - 2021 Jens Gutschmidt

-- (email: opencores@vivare-services.com)

-- 

-- Versions:

-- Revision 1.1210  2021/01/08 22:20:00  jens

-- - Bug Fix rdy_i='0' causes hang after res_res_n_i='0' -> '1'

--   at state RES1/s545 and malfunction of:

--   STA  ABS,Y state s208 -> no write of data

--   STA  (IND,X) state s209 -> no write of data

-- Revision 1.1202  2018/09/10 12:14:00  jens

-- - RESET generates SYNC now, 1 dead cycle delayed

-- Revision 1.1202  RC 2018/09/09 03:00:00  jens

-- - ADC / SBC flags and A like R65C02 now

-- Revision 1.1202  BETA 2018/09/05 19:35:00  jens

-- - BBRx/BBSx internal cycles like real 65C02 now

-- - Bug Fix ADC and SBC in decimal mode (all op codes -

--   1 cycle is missing

-- - Bug Fix ADC and SBC in decimal mode (all op codes -

--   "Overflow" flag was computed wrong)

-- Revision 1.1202  BETA 2018/09/02 18:49:00  jens

-- - Interrupt NMI and IRQ processing via FETCH stage now

-- Revision 1.1202  BETA 2018/08/30 15:39:00  jens

-- - Interrupt priority order is now: BRQ - NMI - IRQ

-- - Performance improvements on-going (Mealy -> Moore)

-- Revision 1.1202  BETA 2018/08/23 20:27:00  jens

-- - Bug Fixes All Branch Instructions 

--   (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS, BRA)

--   3 cycles now if branch forward occur and the branch

--   instruction lies on a xxFEh location.

--   (BBR, BBS) 6 cycles now if branch forward occur and the

--   branch instruction lies on a xxFDh location.

-- - Bug Fix Hardware Interrupts NMI & IRQ - 7 cycles & "SYNC" now

-- - Bug Fix Now all cycles are delayable (WR and internal)

-- 

-- Revision 1.1201  BETA 2014/04/19 14:44:00  jens

-- (never submitted to opencores)

-- - Bug Fix JMP ABS - produced a 6502 like JMP (IND) PCH.

--   When the ABS address data bytes cross the page

--   boundary (e.g. $02FE JMP hhll reads hh from

--   $02FF and ll from $0200, instead $02FF and $0300) 

-- 

-- Revision 1.12  RC 2013/07/31 11:53:00  jens

-- - Bug Fix CMP (IND) - wrongly decoded as function AND

-- - Bug Fix BRK should clear decimal flag P Reg

-- - Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address

-- - Bug Fix Unknown Ops - Used allways 1b2c NOP ($EA) - new NOPs created

-- - Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag was computed wrong)

-- - Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed

-- - Bug Fix RTI - should increment stack pointer (decremented)

-- - Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1" in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates.

-- - Bug Fix ADC and SBC (all op codes - "Overflow" flag was computed wrong)

-- - Bug Fix RMB, SMB Bug - Bit position decoded wrong.

-- 

-- Revision 1.11  2013/07/21 11:11:00  jens

-- - Changing the title block and internal revision history

-- - Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH)

-- 

-- Revision 1.10  2010/02/08 17:34:20  eda

-- BUGFIX for IRQn, NMIn and RTI

-- After detection of NMI or IRQ the address of the next instruction stacked wrong.

-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the

-- vector address is not loaded yet.

-- 

-- 

-- Revision 1.9  2010/02/08 17:32:19  eda

-- BUGFIX for IRQn, NMIn and RTI

-- After detection of NMI or IRQ the address of the next instruction stacked wrong.

-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the

-- vector address is not loaded yet.

-- 

-- 

-- Revision 1.8  2009/01/04 20:23:42  eda

-- *** EMERGENCY BUGFIX ***

-- - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected.

-- - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist

--  when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from

--  $02FF and $0200, instead of $02FF and $0300)

-- 

-- Revision 1.7  2009/01/04 16:54:59  eda

-- - Removed unused bits in ALU (zw_ALUx)

-- 

-- Revision 1.6  2009/01/04 10:27:49  eda

-- Changes for cosmetic issues only

-- 

-- Revision 1.5  2009/01/04 10:25:04  eda

-- Changes for cosmetic issues only

-- 

-- Revision 1.4  2009/01/03 16:53:01  eda

-- - Unused nets and blocks deleted

-- - Re-arragend symbols in block FSM_Execution_Unit

-- - Renamed blocks

-- - Input SO implemented

-- 

-- Revision 1.3  2009/01/03 16:42:02  eda

-- - Unused nets and blocks deleted

-- - Re-arragend symbols in block FSM_Execution_Unit

-- - Renamed blocks

-- - Input SO implemented

-- 

-- Revision 1.2  2008/12/31 19:31:24  eda

-- Production Release

--  

-- 

--

-- r65c02_tc.fsm_execution_unit.fsm

--

-- Date:    09.01.2021

-- Time:    17:10:06

-- By:        VIVARE GmbH, Switzerland

--

-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt

-- 

-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.

-- 

-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.

-- 

-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.

-- 

-- 

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

architecture fsm of fsm_execution_unit is

   -- Architecture Declarations

   signal reg_F : std_logic_vector( 7 DOWNTO 0 );

   signal reg_PC : std_logic_vector(15 DOWNTO 0);

   signal reg_PC1 : std_logic_vector( 15 DOWNTO 0 );

   signal reg_sel_pc_in : std_logic;

   signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );

   signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );

   signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );

   signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );

   signal reg_sel_sp_as : std_logic;

   signal reg_sel_sp_in : std_logic;

   signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );

   signal sig_PC : std_logic_vector(15 DOWNTO 0);

   signal sig_RD : std_logic;

   signal sig_RWn : std_logic;

   signal sig_SYNC : std_logic;

   signal sig_WR : std_logic;

   signal zw_100_a : std_logic;

   signal zw_100_alu : std_logic;

   signal zw_100_d : std_logic;

   signal zw_50_a : std_logic;

   signal zw_50_alu : std_logic;

   signal zw_50_d : std_logic;

   signal zw_ALU : std_logic_vector(9 DOWNTO 0);

   signal zw_ALU1 : std_logic_vector(9 DOWNTO 0);

   signal zw_ALU2 : std_logic_vector(9 DOWNTO 0);

   signal zw_ALU3 : std_logic_vector(9 DOWNTO 0);

   signal zw_ALU4 : std_logic_vector(9 DOWNTO 0);

   signal zw_ALU5 : std_logic_vector(9 DOWNTO 0);

   signal zw_ALU6 : std_logic_vector(9 DOWNTO 0);

   signal zw_PC : std_logic_vector( 15 DOWNTO 0 );

   signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 );

   signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );

   signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0);

   signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_so : std_logic;

   signal zw_w1 : std_logic_vector( 15 DOWNTO 0 );

   signal zw_w2 : std_logic_vector( 15 DOWNTO 0 );

   signal zw_w3 : std_logic_vector( 15 DOWNTO 0 );

   subtype state_type is

      std_logic_vector(7 downto 0);

   -- State vector declaration

   attribute state_vector : string;

   attribute state_vector of fsm : architecture is "current_state";

   -- Hard encoding

   constant s544 : state_type := "00000000";

   constant s545 : state_type := "00000001";

   constant s546 : state_type := "00000011";

   constant s547 : state_type := "00000010";

   constant s549 : state_type := "00000110";

   constant s550 : state_type := "00000111";

   constant RES : state_type := "00000101";

   constant FETCH : state_type := "00000100";

   constant s6 : state_type := "00001100";

   constant s7 : state_type := "00001101";

   constant s8 : state_type := "00001111";

   constant s9 : state_type := "00001110";

   constant s10 : state_type := "00001010";

   constant s13 : state_type := "00001011";

   constant s18 : state_type := "00001001";

   constant s19 : state_type := "00001000";

   constant s26 : state_type := "00011000";

   constant s27 : state_type := "00011001";

   constant s203 : state_type := "00011011";

   constant s204 : state_type := "00011010";

   constant s212 : state_type := "00011110";

   constant s216 : state_type := "00011111";

   constant s219 : state_type := "00011101";

   constant s220 : state_type := "00011100";

   constant s227 : state_type := "00010100";

   constant s228 : state_type := "00010101";

   constant s230 : state_type := "00010111";

   constant s231 : state_type := "00010110";

   constant s229 : state_type := "00010010";

   constant s512 : state_type := "00010011";

   constant s554 : state_type := "00010001";

   constant s578 : state_type := "00010000";

   constant s581 : state_type := "00110000";

   constant s582 : state_type := "00110001";

   constant s583 : state_type := "00110011";

   constant s584 : state_type := "00110010";

   constant s585 : state_type := "00110110";

   constant s586 : state_type := "00110111";

   constant s587 : state_type := "00110101";

   constant s580 : state_type := "00110100";

   constant s178 : state_type := "00111100";

   constant s194 : state_type := "00111101";

   constant s195 : state_type := "00111111";

   constant s196 : state_type := "00111110";

   constant s197 : state_type := "00111010";

   constant s198 : state_type := "00111011";

   constant s199 : state_type := "00111001";

   constant s200 : state_type := "00111000";

   constant s205 : state_type := "00101000";

   constant s206 : state_type := "00101001";

   constant s207 : state_type := "00101011";

   constant s208 : state_type := "00101010";

   constant s209 : state_type := "00101110";

   constant s213 : state_type := "00101111";

   constant s214 : state_type := "00101101";

   constant s513 : state_type := "00101100";

   constant s588 : state_type := "00100100";

   constant s589 : state_type := "00100101";

   constant s590 : state_type := "00100111";

   constant s591 : state_type := "00100110";

   constant s592 : state_type := "00100010";

   constant s593 : state_type := "00100011";

   constant s594 : state_type := "00100001";

   constant s595 : state_type := "00100000";

   constant s596 : state_type := "01100000";

   constant s597 : state_type := "01100001";

   constant s405 : state_type := "01100011";

   constant s408 : state_type := "01100010";

   constant s410 : state_type := "01100110";

   constant s411 : state_type := "01100111";

   constant s414 : state_type := "01100101";

   constant s415 : state_type := "01100100";

   constant s417 : state_type := "01101100";

   constant s419 : state_type := "01101101";

   constant s420 : state_type := "01101111";

   constant s598 : state_type := "01101110";

   constant s599 : state_type := "01101010";

   constant s600 : state_type := "01101011";

   constant s268 : state_type := "01101001";

   constant s305 : state_type := "01101000";

   constant s306 : state_type := "01111000";

   constant jmp1 : state_type := "01111001";

   constant jmp2_1 : state_type := "01111011";

   constant jmp4_12 : state_type := "01111010";

   constant jmp_ex : state_type := "01111110";

   constant jmp2_2 : state_type := "01111111";

   constant jmp3_1 : state_type := "01111101";

   constant s402 : state_type := "01111100";

   constant s421 : state_type := "01110100";

   constant s422 : state_type := "01110101";

   constant s423 : state_type := "01110111";

   constant s424 : state_type := "01110110";

   constant s362 : state_type := "01110010";

   constant s221 : state_type := "01110011";

   constant s232 : state_type := "01110001";

   constant s233 : state_type := "01110000";

   constant s234 : state_type := "01010000";

   constant s235 : state_type := "01010001";

   constant brk1 : state_type := "01010011";

   constant brk2 : state_type := "01010010";

   constant brk3 : state_type := "01010110";

   constant brk4 : state_type := "01010111";

   constant brk6 : state_type := "01010101";

   constant brk5 : state_type := "01010100";

   constant s425 : state_type := "01011100";

   constant s426 : state_type := "01011101";

   constant s427 : state_type := "01011111";

   constant s428 : state_type := "01011110";

   constant s429 : state_type := "01011010";

   constant s430 : state_type := "01011011";

   constant s431 : state_type := "01011001";

   constant s432 : state_type := "01011000";

   constant s433 : state_type := "01001000";

   constant s434 : state_type := "01001001";

   constant s236 : state_type := "01001011";

   constant s245 : state_type := "01001010";

   constant s246 : state_type := "01001110";

   constant s248 : state_type := "01001111";

   constant s345 : state_type := "01001101";

   constant s346 : state_type := "01001100";

   constant s252 : state_type := "01000100";

   constant s253 : state_type := "01000101";

   constant s435 : state_type := "01000111";

   constant s436 : state_type := "01000110";

   constant s437 : state_type := "01000010";

   constant s438 : state_type := "01000011";

   constant s439 : state_type := "01000001";

   constant s440 : state_type := "01000000";

   constant s441 : state_type := "11000000";

   constant s442 : state_type := "11000001";

   constant s443 : state_type := "11000011";

   constant s444 : state_type := "11000010";

   constant irq1 : state_type := "11000110";

   constant irq2 : state_type := "11000111";

   constant irq3 : state_type := "11000101";

   constant irq5b : state_type := "11000100";

   constant irq5a : state_type := "11001100";

   constant irq4 : state_type := "11001101";

   constant irq6 : state_type := "11001111";

   constant s11 : state_type := "11001110";

   constant s12 : state_type := "11001010";

   constant s20 : state_type := "11001011";

   constant s14 : state_type := "11001001";

   constant s21 : state_type := "11001000";

   constant s23 : state_type := "11011000";

   constant s15 : state_type := "11011001";

   constant s25 : state_type := "11011011";

   constant s28 : state_type := "11011010";

   constant s16 : state_type := "11011110";

   constant s30 : state_type := "11011111";

   constant s31 : state_type := "11011101";

   constant s32 : state_type := "11011100";

   constant s33 : state_type := "11010100";

   constant s34 : state_type := "11010101";

   constant s36 : state_type := "11010111";

   constant jmp3_2 : state_type := "11010110";

   constant s601 : state_type := "11010010";

   constant s602 : state_type := "11010011";

   constant s270 : state_type := "11010001";

   constant s307 : state_type := "11010000";

   constant s308 : state_type := "11110000";

   constant s271 : state_type := "11110001";

   constant s272 : state_type := "11110011";

   constant s309 : state_type := "11110010";

   constant RES7 : state_type := "11110110";

   -- Declare current and next state signals

   signal current_state : state_type;

   signal next_state : state_type;

   -- Declare any pre-registered internal signals

   signal d_o_cld : std_logic_vector ( 7 downto 0 );

   signal rd_o_cld : std_logic ;

   signal sync_o_cld : std_logic ;

   signal wr_n_o_cld : std_logic ;

   signal wr_o_cld : std_logic ;

begin

   -----------------------------------------------------------------

   clocked_proc : process (

      clk_clk_i,

      rst_rst_n_i

   )

   -----------------------------------------------------------------

   begin

      if (rst_rst_n_i = '0') then

         current_state <= RES;

         -- Default Reset Values

         d_o_cld <= X"00";

         rd_o_cld <= '1';

         sync_o_cld <= '0';

         wr_n_o_cld <= '1';

         wr_o_cld <= '0';

         reg_F <= "00110100";

         reg_PC <= X"0000";

         reg_PC1 <= X"0000";

         reg_sel_pc_in <= '0';

         reg_sel_pc_val <= "00";

         reg_sel_rb_in <= "00";

         reg_sel_rb_out <= "00";

         reg_sel_reg <= "00";

         reg_sel_sp_as <= '0';

         reg_sel_sp_in <= '0';

         sig_PC <= X"0000";

         zw_PC <= X"0000";

         zw_REG_ALU <= '0' & X"00";

         zw_REG_OP <= X"00";

         zw_REG_sig_PC <= X"0000";

         zw_b1 <= X"00";

         zw_b2 <= X"00";

         zw_b3 <= X"00";

         zw_b4 <= X"00";

         zw_so <= '0';

         zw_w1 <= X"0000";

         zw_w2 <= X"0000";

         zw_w3 <= X"0000";

      elsif (clk_clk_i'event and clk_clk_i = '1') then

         current_state <= next_state;

         -- Default Assignment To Internals

         reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);

         reg_PC <= reg_PC;

         reg_PC1 <= reg_PC1;

         reg_sel_pc_in <= reg_sel_pc_in;

         reg_sel_pc_val <= reg_sel_pc_val;

         reg_sel_rb_in <= reg_sel_rb_in;

         reg_sel_rb_out <= reg_sel_rb_out;

         reg_sel_reg <= reg_sel_reg;

         reg_sel_sp_as <= reg_sel_sp_as;

         reg_sel_sp_in <= reg_sel_sp_in;

         sig_PC <= sig_PC;

         zw_PC <= zw_PC;

         zw_REG_ALU <= zw_REG_ALU;

         zw_REG_OP <= zw_REG_OP;

         zw_REG_sig_PC <= zw_REG_sig_PC;

         zw_b1 <= zw_b1;

         zw_b2 <= zw_b2;

         zw_b3 <= zw_b3;

         zw_b4 <= zw_b4;

         zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));

         zw_w1 <= zw_w1;

         zw_w2 <= zw_w2;

         zw_w3 <= zw_w3;

         d_o_cld <= sig_D_OUT;

         rd_o_cld <= sig_RD;

         sync_o_cld <= sig_SYNC;

         wr_n_o_cld <= sig_RWn;

         wr_o_cld <= sig_WR;

         -- Combined Actions

         case current_state is

            when s544 =>

               if (rdy_i = '1') then

                  sig_PC <= adr_sp_i;

               end if;

            when s545 =>

               if (rdy_i = '1') then

                  sig_PC <= adr_sp_i;

                  reg_sel_pc_in <= '0';

                  reg_sel_pc_val <= "00";

               end if;

            when s546 =>

               if (rdy_i = '1') then

                  sig_PC <= adr_pc_i;

               end if;

            when s547 =>

               zw_w1 (7 downto 0) <= d_i;

               if (rdy_i = '1') then

                  sig_PC <= adr_pc_i;

                  reg_sel_pc_in <= '1';

                  reg_sel_pc_val <= "11";

               end if;

            when s549 =>

               reg_F(2) <= '1';

               reg_F(3) <= '0';

               reg_F(5) <= '1';

               if (rdy_i = '1') then

                  sig_PC  <= d_i & zw_w1 (7 downto 0);

                  reg_sel_pc_in <= '0';

                  reg_sel_pc_val <= "00";

                  reg_sel_sp_in <= '0';

                  reg_sel_sp_as <= '1';

               end if;

            when s550 =>

               if (rdy_i = '1') then

                  sig_PC <= adr_sp_i;

                  reg_sel_pc_in <= '1';

                  reg_sel_pc_val <= "00";

               end if;

            when RES =>

               reg_sel_pc_in <= '0';

               reg_sel_pc_val <= "00";

            when FETCH =>

               zw_REG_OP <= d_i;

               if ((d_i = X"00") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((nmi_i = '1') and (rdy_i = '1')) then

                  reg_sel_pc_in <= '0';

                  reg_sel_pc_val <= "00";

                  reg_sel_sp_in <= '0';

                  reg_sel_sp_as <= '1';

                  sig_PC <= adr_nxt_pc_i;

                  zw_w3 <= adr_pc_i;

               elsif ((irq_n_i = '0' and

                      reg_F(2) = '0') and (rdy_i = '1')) then

                  reg_sel_pc_in <= '0';

                  reg_sel_pc_val <= "00";

                  reg_sel_sp_in <= '0';

                  reg_sel_sp_as <= '1';

                  sig_PC <= adr_nxt_pc_i;

                  zw_w3 <= adr_pc_i;

               elsif ((d_i = X"58") and (rdy_i = '1')) then

               elsif ((d_i = X"28") and (rdy_i = '1')) then

                  reg_sel_sp_in <= '0';

                  reg_sel_sp_as <= '0';

               elsif ((d_i = X"78") and (rdy_i = '1')) then

               elsif ((d_i = X"69" or

                      d_i = X"65" or

                      d_i = X"75" or

                      d_i = X"6D" or

                      d_i = X"7D" or

                      d_i = X"79" or

                      d_i = X"61" or

                      d_i = X"71" or

                      d_i = X"72") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

                  reg_sel_reg <= "00";

                  reg_sel_rb_in <= "11";

               elsif ((d_i = X"06" or

                      d_i = X"16" or

                      d_i = X"0E" or

                      d_i = X"1E" or

                      d_i (3 downto 0) = X"7" or

                      d_i = X"14" or

                      d_i = X"04" or

                      d_i = X"0C" or

                      d_i = X"1C") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"90" or

                      d_i = X"B0" or

                      d_i = X"F0" or

                      d_i = X"30" or

                      d_i = X"D0" or

                      d_i = X"10" or

                      d_i = X"50" or

                      d_i = X"70" or

                      d_i = X"80") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"24" or

                      d_i = X"2C" or

                      d_i = X"3C" or

                      d_i = X"34" or

                      d_i = X"89") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"18") and (rdy_i = '1')) then

               elsif ((d_i = X"D8") and (rdy_i = '1')) then

               elsif ((d_i = X"8F" or

                      d_i = X"9F" or

                      d_i = X"AF" or

                      d_i = X"BF" or

                      d_i = X"CF" or

                      d_i = X"DF" or

                      d_i = X"EF" or

                      d_i = X"FF" or

                      d_i = X"0F" or

                      d_i = X"1F" or

                      d_i = X"2F" or

                      d_i = X"3F" or

                      d_i = X"4F" or

                      d_i = X"5F" or

                      d_i = X"6F" or

                      d_i = X"7F") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"B8") and (rdy_i = '1')) then

               elsif ((d_i = X"E0" or