Subversion Repositories cpu65c02_true_cycle

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

entity fsm_execution_unit is

   port(

      adr_nxt_pc_i : in     std_logic_vector (15 downto 0);

      adr_pc_i     : in     std_logic_vector (15 downto 0);

      adr_sp_i     : in     std_logic_vector (15 downto 0);

      clk_clk_i    : in     std_logic;

      d_alu_i      : in     std_logic_vector ( 7 downto 0 );

      d_alu_prio_i : in     std_logic_vector (7 downto 0);

      d_i          : in     std_logic_vector ( 7 downto 0 );

      d_regs_out_i : in     std_logic_vector ( 7 downto 0 );

      irq_n_i      : in     std_logic;

      nmi_i        : in     std_logic;

      q_a_i        : in     std_logic_vector ( 7 downto 0 );

      q_x_i        : in     std_logic_vector ( 7 downto 0 );

      q_y_i        : in     std_logic_vector ( 7 downto 0 );

      rdy_i        : in     std_logic;

      reg_0flag_i  : in     std_logic;

      reg_1flag_i  : in     std_logic;

      reg_7flag_i  : in     std_logic;

      rst_rst_n_i  : in     std_logic;

      so_n_i       : in     std_logic;

      a_o          : out    std_logic_vector (15 downto 0);

      adr_o        : out    std_logic_vector (15 downto 0);

      ch_a_o       : out    std_logic_vector ( 7 downto 0 );

      ch_b_o       : out    std_logic_vector ( 7 downto 0 );

      d_o          : out    std_logic_vector ( 7 downto 0 );

      d_regs_in_o  : out    std_logic_vector ( 7 downto 0 );

      ld_o         : out    std_logic_vector ( 1 downto 0 );

      ld_pc_o      : out    std_logic;

      ld_sp_o      : out    std_logic;

      load_regs_o  : out    std_logic;

      offset_o     : out    std_logic_vector ( 15 downto 0 );

      rd_o         : out    std_logic;

      rst_nmi_o    : out    std_logic;

      sel_pc_in_o  : out    std_logic;

      sel_pc_val_o : out    std_logic_vector ( 1 downto 0 );

      sel_rb_in_o  : out    std_logic_vector ( 1 downto 0 );

      sel_rb_out_o : out    std_logic_vector ( 1 downto 0 );

      sel_reg_o    : out    std_logic_vector ( 1 downto 0 );

      sel_sp_as_o  : out    std_logic;

      sel_sp_in_o  : out    std_logic;

      sync_o       : out    std_logic;

      wr_n_o       : out    std_logic;

      wr_o         : out    std_logic

   );

-- Declarations

end fsm_execution_unit ;

-- (C) 2008 - 2021 Jens Gutschmidt

-- (email: opencores@vivare-services.com)

-- 

-- Versions:

-- Revision 1.15  2021/01/22 13:24:00  jens

-- Production Release

-- 

-- Revision 1.14  2021/01/10 17:56:00  jens

-- - Performance improvements

-- Revision 1.13  2018/10/14 11:50:00  jens

-- - Performance improvements

-- Revision 1.1202  2018/09/10 12:14:00  jens

-- - RESET generates SYNC now, 1 dead cycle delayed

-- Revision 1.1202  RC 2018/09/09 03:00:00  jens

-- - ADC / SBC flags and A like R65C02 now

-- Revision 1.1202  BETA 2018/09/05 19:35:00  jens

-- - BBRx/BBSx internal cycles like real 65C02 now

-- - Bug Fix ADC and SBC in decimal mode (all op codes -

--   1 cycle is missing

-- - Bug Fix ADC and SBC in decimal mode (all op codes -

--   "Overflow" flag was computed wrong)

-- Revision 1.1202  BETA 2018/09/02 18:49:00  jens

-- - Interrupt NMI and IRQ processing via FETCH stage now

-- Revision 1.1202  BETA 2018/08/30 15:39:00  jens

-- - Interrupt priority order is now: BRQ - NMI - IRQ

-- - Performance improvements on-going (Mealy -> Moore)

-- Revision 1.1202  BETA 2018/08/23 20:27:00  jens

-- - Bug Fixes All Branch Instructions 

--   (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS, BRA)

--   3 cycles now if branch forward occur and the branch

--   instruction lies on a xxFEh location.

--   (BBR, BBS) 6 cycles now if branch forward occur and the

--   branch instruction lies on a xxFDh location.

-- - Bug Fix Hardware Interrupts NMI & IRQ - 7 cycles & "SYNC" now

-- - Bug Fix Now all cycles are delayable (WR and internal)

-- 

-- Revision 1.1201  BETA 2014/04/19 14:44:00  jens

-- (never submitted to opencores)

-- - Bug Fix JMP ABS - produced a 6502 like JMP (IND) PCH.

--   When the ABS address data bytes cross the page

--   boundary (e.g. $02FE JMP hhll reads hh from

--   $02FF and ll from $0200, instead $02FF and $0300) 

-- 

-- Revision 1.12  RC 2013/07/31 11:53:00  jens

-- - Bug Fix CMP (IND) - wrongly decoded as function AND

-- - Bug Fix BRK should clear decimal flag P Reg

-- - Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address

-- - Bug Fix Unknown Ops - Used allways 1b2c NOP ($EA) - new NOPs created

-- - Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag was computed wrong)

-- - Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed

-- - Bug Fix RTI - should increment stack pointer (decremented)

-- - Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1" in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates.

-- - Bug Fix ADC and SBC (all op codes - "Overflow" flag was computed wrong)

-- - Bug Fix RMB, SMB Bug - Bit position decoded wrong.

-- 

-- Revision 1.11  2013/07/21 11:11:00  jens

-- - Changing the title block and internal revision history

-- - Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH)

-- 

-- Revision 1.10  2010/02/08 17:34:20  eda

-- BUGFIX for IRQn, NMIn and RTI

-- After detection of NMI or IRQ the address of the next instruction stacked wrong.

-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the

-- vector address is not loaded yet.

-- 

-- 

-- Revision 1.9  2010/02/08 17:32:19  eda

-- BUGFIX for IRQn, NMIn and RTI

-- After detection of NMI or IRQ the address of the next instruction stacked wrong.

-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the

-- vector address is not loaded yet.

-- 

-- 

-- Revision 1.8  2009/01/04 20:23:42  eda

-- *** EMERGENCY BUGFIX ***

-- - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected.

-- - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist

--  when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from

--  $02FF and $0200, instead of $02FF and $0300)

-- 

-- Revision 1.7  2009/01/04 16:54:59  eda

-- - Removed unused bits in ALU (zw_ALUx)

-- 

-- Revision 1.6  2009/01/04 10:27:49  eda

-- Changes for cosmetic issues only

-- 

-- Revision 1.5  2009/01/04 10:25:04  eda

-- Changes for cosmetic issues only

-- 

-- Revision 1.4  2009/01/03 16:53:01  eda

-- - Unused nets and blocks deleted

-- - Re-arragend symbols in block FSM_Execution_Unit

-- - Renamed blocks

-- - Input SO implemented

-- 

-- Revision 1.3  2009/01/03 16:42:02  eda

-- - Unused nets and blocks deleted

-- - Re-arragend symbols in block FSM_Execution_Unit

-- - Renamed blocks

-- - Input SO implemented

-- 

-- Revision 1.2  2008/12/31 19:31:24  eda

-- Production Release

--  

-- 

-- (C) 2008 - 2021 Jens Gutschmidt

-- (email: opencores@vivare-services.com)

-- 

-- Versions:

-- Revision 1.13 2021/01/22 13:23:00  jens

-- Production Release

-- Revision 1.1207 2021/01/05 23:36:00  jens

-- - Bug Fixes RDY (='0') 

-- - Performance improvements

-- Revision 1.02  2020/12/31 17:22:00  jens

-- - Bug Fix RDY (='0') forces A, X, Y and flags

--   to be comulated at specific states on several

--   instructions.

-- Revision 1.01  2018/10/14 11:57:00  jens

-- Initial Version

--  

-- 

-- (C) 2008 - 2021 Jens Gutschmidt

-- (email: opencores@vivare-services.com)

-- 

-- Versions:

-- Revision 1.01  2018/09/26 11:11:00  jens

-- Production Release

--  

-- 

-- (C) 2008 - 2021 Jens Gutschmidt

-- (email: opencores@vivare-services.com)

-- 

-- Versions:

-- Revision 1.01  2018/09/26 11:11:00  jens

-- Production Release

--  

-- 

-- (C) 2008 - 2021 Jens Gutschmidt

-- (email: opencores@vivare-services.com)

-- 

-- Versions:

-- Revision 1.01  2018/09/26 11:11:00  jens

-- Production Release

--  

-- 

-- (C) 2008 - 2021 Jens Gutschmidt

-- (email: opencores@vivare-services.com)

-- 

-- Versions:

-- Revision 1.01  2018/10/02 10:36:00  jens

-- Production Release

--  

-- 

--

-- r65c02_tc.fsm_execution_unit.fsm

--

-- Date:    22.01.2021

-- Time:    14:49:40

-- By:        VIVARE GmbH, Switzerland

--

-- COPYRIGHT (C) 2008 - 2021 by Jens Gutschmidt

-- 

-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.

-- 

-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.

-- 

-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.

-- 

-- 

-- COPYRIGHT (C) 2008 - 2021 by Jens Gutschmidt

-- 

-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.

-- 

-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.

-- 

-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.

-- 

-- 

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

architecture fsm of fsm_execution_unit is

   -- Architecture Declarations

   signal adc_sbc_finished : std_logic;

   signal c_detect_out : std_logic;

   signal cnz_detect_in : std_logic_vector(8 DOWNTO 0);

   signal d_regs_out_bak_i : std_logic_vector( 7 DOWNTO 0 );

   signal irq_finished : std_logic;

   signal n_detect_out : std_logic;

   signal op_fetch : std_logic;

   signal op_finished : std_logic;

   signal op_finished_det : std_logic;

   signal q_a_bak_i : std_logic_vector( 7 DOWNTO 0 );

   signal q_x_bak_i : std_logic_vector( 7 DOWNTO 0 );

   signal q_y_bak_i : std_logic_vector( 7 DOWNTO 0 );

   signal reg_F : std_logic_vector( 7 DOWNTO 0 );

   signal reg_F_bak : std_logic_vector( 7 DOWNTO 0 );

   signal reg_op_finished : std_logic;

   signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );

   signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );

   signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );

   signal rmb_started : std_logic;

   signal rst_finished : std_logic;

   signal sel_pc_in : std_logic;

   signal sel_pc_val : std_logic_vector( 1 DOWNTO 0 );

   signal sel_sp_as : std_logic;

   signal sel_sp_in : std_logic;

   signal shift_rot_asl_out : std_logic_vector( 7 DOWNTO 0 );

   signal shift_rot_in : std_logic_vector( 7 DOWNTO 0 );

   signal shift_rot_l_c_out : std_logic;

   signal shift_rot_lsr_out : std_logic_vector( 7 DOWNTO 0 );

   signal shift_rot_r_c_out : std_logic;

   signal shift_rot_rol_out : std_logic_vector( 7 DOWNTO 0 );

   signal shift_rot_ror_out : std_logic_vector( 7 DOWNTO 0 );

   signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );

   signal sig_PC : std_logic_vector(15 DOWNTO 0);

   signal sig_RD : std_logic;

   signal sig_RWn : std_logic;

   signal sig_SYNC : std_logic;

   signal sig_WR : std_logic;

   signal z_detect_out : std_logic;

   signal zw_ALU : std_logic_vector(9 DOWNTO 0);

   signal zw_ALU1 : std_logic_vector(9 DOWNTO 0);

   signal zw_ALU2 : std_logic_vector(9 DOWNTO 0);

   signal zw_ALU3 : std_logic_vector(9 DOWNTO 0);

   signal zw_ALU4 : std_logic_vector(9 DOWNTO 0);

   signal zw_ALU5 : std_logic_vector(9 DOWNTO 0);

   signal zw_ALU6 : std_logic_vector(9 DOWNTO 0);

   signal zw_PC : std_logic_vector( 15 DOWNTO 0 );

   signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 );

   signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );

   signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0);

   signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b10 : std_logic_vector(9 DOWNTO 0);

   signal zw_b11 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b12 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b13 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b14 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b5 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b6 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b7 : std_logic_vector(9 DOWNTO 0);

   signal zw_b8 : std_logic_vector(9 DOWNTO 0);

   signal zw_b9 : std_logic_vector(9 DOWNTO 0);

   signal zw_din : std_logic_vector(7 DOWNTO 0);

   signal zw_reg_0flag : std_logic;

   signal zw_so : std_logic;

   signal zw_w1 : std_logic_vector( 15 DOWNTO 0 );

   signal zw_w2 : std_logic_vector( 15 DOWNTO 0 );

   signal zw_w3 : std_logic_vector( 15 DOWNTO 0 );

   type csm_state_type is (

      res2,

      res4,

      res5,

      res6,

      res7,

      res3,

      RES,

      FETCH,

      nop1,

      txs1,

      bxx1,

      bxx2,

      bxx3,

      jmp1,

      jmp2_1,

      jmp4_12,

      jmp_ex,

      jmp2_2,

      jmp3_1,

      jsr1,

      jsr2,

      jsr3,

      jsr4,

      jsr5,

      brk1,

      brk2,

      brk3,

      brk4,

      brk6,

      brk5,

      rti1,

      rti2,

      rti3,

      rti4,

      rti5,

      rts1,

      rts2,

      rts3,

      rts4,

      rts5,

      pha1,

      pha2,

      php1,

      php2,

      pla1,

      pla2,

      pla3,

      plp1,

      plp2,

      plp3,

      irq1,

      irq2,

      irq3,

      irq5b,

      irq5a,

      irq4,

      irq6a,

      nop22,

      nop231,

      nop232,

      nop241,

      nop242,

      nop243,

      nop341,

      nop342,

      nop343,

      nop381,

      nop382,

      nop383,

      nop384,

      nop387,

      nop385,

      nop386,

      jmp3_2,

      bbr1,

      bbr5,

      bbr4,

      bbr2,

      bbr3,

      bbr6,

      RES0,

      zp1,

      zp2,

      zpx1,

      zpx2,

      zpx3,

      ab1,

      ab2,

      ab3,

      absx1,

      absx2,

      absx4,

      absx3,

      ind1,

      ind3,

      ind4,

      ind2,

      indy1,

      indy2,

      indy3,

      indy5,

      indy4,

      indx1,

      indx4,

      indx2,

      indx3,

      indx5,

      zpy1,

      zpy2,

      zpy3,

      absy2,

      absy1,

      absy4,

      absy3,

      imm1,

      imp1,

      irq6b,

      absx5,

      absy5,

      indy6,

      zprmw1,

      zprmw2,

      zprmw31,

      zprmw41,

      zpxrmw1,

      zpxrmw2,

      zpxrmw3,

      zpxrmw41,

      zpxrmw51,

      abrmw1,

      abrmw2,

      abrmw3,

      abrmw41,

      abrmw51,

      abxrmb1,

      abxrmb2,

      abxrmb3,

      abxrmb41,

      abxrmb51,

      abxrmb61,

      zp2w,

      zpx3w,

      zpy3w,

      ab3w,

      absx4w,

      absx3w,

      absy4w,

      absy3w,

      ind4w,

      indx5w,

      indy5w,

      indy4w,

      zprmw32,

      zpxrmw42,

      abrmw42,

      abxrmb52,

      abxrmb42,

      zp3,

      zpx4,

      ab4,

      ind5,

      indx6,

      imm2

   );

   type csm_functions_state_type is (

      f_idle,

      f_and,

      f_lda,

      f_rst,

      f_eor,

      f_cmp,

      f_ora,

      f_clc,

      f_sec,

      f_cld,

      f_sed,

      f_clv,

      f_cli,

      f_sei,

      f_rti,

      f_irq,

      f_res,

      f_bit1,

      f_bit2,

      f_de_in_a,

      f_adc_bin,

      f_sbc_bin,

      f_adc_dec,

      f_adc_dec1,

      f_sbc_dec,

      f_sbc_dec1,

      f_asla,

      f_lsra,

      f_rola,

      f_rora,

      f_tax,

      f_tsx,

      f_decr,

      f_asl,

      f_lsr,

      f_rol,

      f_ror,

      f_rmb,

      f_smb,

      f_trb,

      f_tsb

   );

   type csm_rb_out_state_type is (

      rb_out_idle,

      rb_out_01,

      rb_out_10,

      rb_out_11

   );

   type csm_reg_state_type is (

      reg_idle,

      reg_10,

      reg_11,

      reg_01

   );

   type csm_rb_in_state_type is (

      rb_in_idle,

      rb_in_01,

      rb_in_10,

      rb_in_00

   );

   type csm_add_value_state_type is (

      add_val_idle,

      add_val

   );

   -- Declare current and next state signals

   signal csm_current_state : csm_state_type;

   signal csm_next_state : csm_state_type;

   signal csm_functions_current_state : csm_functions_state_type;

   signal csm_functions_next_state : csm_functions_state_type;

   signal csm_rb_out_current_state : csm_rb_out_state_type;

   signal csm_rb_out_next_state : csm_rb_out_state_type;

   signal csm_reg_current_state : csm_reg_state_type;

   signal csm_reg_next_state : csm_reg_state_type;

   signal csm_rb_in_current_state : csm_rb_in_state_type;

   signal csm_rb_in_next_state : csm_rb_in_state_type;

   signal csm_add_value_current_state : csm_add_value_state_type;

   signal csm_add_value_next_state : csm_add_value_state_type;

   -- Declare any pre-registered internal signals

   signal sync_o_cld : std_logic ;

begin

   -----------------------------------------------------------------

   csm_clocked_proc : process (

      clk_clk_i,

      rst_rst_n_i

   )

   -----------------------------------------------------------------

   begin

      if (rst_rst_n_i = '0') then

         csm_current_state <= RES;

         -- Default Reset Values

         sync_o_cld <= '0';

         reg_op_finished <= '0';

         reg_sel_rb_in <= "00";

         reg_sel_rb_out <= "00";

         reg_sel_reg <= "00";

         zw_PC <= X"0000";

         zw_REG_ALU <= '0' & X"00";

         zw_REG_OP <= X"00";

         zw_REG_sig_PC <= X"0000";

         zw_b1 <= X"00";

         zw_b11 <= X"00";

         zw_b12 <= X"00";

         zw_b2 <= X"00";

         zw_b3 <= X"00";

         zw_b5 <= X"00";

         zw_b6 <= X"00";

         zw_reg_0flag <= '0';

         zw_so <= '0';

         zw_w1 <= X"0000";

         zw_w2 <= X"0000";

         zw_w3 <= X"0000";

      elsif (clk_clk_i'event and clk_clk_i = '1') then

         csm_current_state <= csm_next_state;

         -- Default Assignment To Internals

         reg_op_finished <= op_finished;

         reg_sel_rb_in <= reg_sel_rb_in;

         reg_sel_rb_out <= reg_sel_rb_out;

         reg_sel_reg <= reg_sel_reg;

         zw_PC <= zw_PC;

         zw_REG_ALU <= zw_REG_ALU;

         zw_REG_OP <= zw_REG_OP;

         zw_REG_sig_PC <= zw_REG_sig_PC;

         zw_b1 <= zw_b1;

         zw_b11 <= zw_b11;

         zw_b12 <= zw_b12;

         zw_b2 <= zw_b2;

         zw_b3 <= zw_b3;

         zw_b5 <= zw_b5;

         zw_b6 <= zw_b6;

         zw_reg_0flag <= zw_reg_0flag;

         zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));

         zw_w1 <= zw_w1;

         zw_w2 <= zw_w2;

         zw_w3 <= zw_w3;

         sync_o_cld <= sig_SYNC;

         -- Combined Actions

         case csm_current_state is

            when res6 =>

               zw_b5 <= d_i;

            when FETCH =>

               zw_REG_OP <= d_i;

               if ((d_i = X"00") and (rdy_i = '1')) then

               elsif ((nmi_i = '1') and (rdy_i = '1')) then

                  zw_w3 <= adr_pc_i;

               elsif ((irq_n_i = '0' and

                      reg_F(2) = '0') and (rdy_i = '1')) then

                  zw_w3 <= adr_pc_i;

               end if;

            when bxx1 =>

               zw_b3 <= adr_nxt_pc_i (15 downto 8);

               zw_b2 <= d_i;

            when jmp1 =>

               zw_b5 <= d_i;

            when jmp2_1 =>

               zw_b6 <= d_i;

            when jmp4_12 =>

               zw_b5 <= d_i;

            when jmp2_2 =>

               zw_b6 <= d_i;

            when jsr1 =>

               zw_b1 <= d_i;

            when jsr2 =>

               zw_b11 <= adr_pc_i (15 downto 8);

               zw_b12 <= adr_pc_i (7 downto 0);

            when brk1 =>

               zw_b11 <= adr_nxt_pc_i (15 downto 8);

               zw_b12 <= adr_nxt_pc_i (7 downto 0);

            when brk3 =>

               zw_b11 <= reg_F OR X"30";

            when brk5 =>

               zw_b5 <= d_i;

            when rti4 =>

               zw_b5 <= d_i;

            when rts3 =>

               zw_b5 <= d_i;

            when rts4 =>

               zw_b6 <= d_i;

            when irq1 =>

               zw_b11 <= zw_w3 (15 downto 8);

               zw_b12 <= zw_w3 (7 downto 0);

            when irq3 =>

               zw_b11 <= reg_F AND X"EF";

            when irq5b =>

               zw_b5 <= d_i;

            when irq5a =>

               zw_b5 <= d_i;

            when bbr1 =>

               zw_b2 <= d_i;

            when bbr4 =>

               zw_w3 <= adr_pc_i;

               zw_b2 <= d_i;

               zw_b3 <= adr_nxt_pc_i (15 downto 8);

            when bbr3 =>

               zw_b1 <= d_i;

            when zp1 =>

               zw_b5 <= d_i;

               zw_b11 <= d_regs_out_i;

            when zpx1 =>

               zw_b5 <= d_i;

               zw_b11 <= d_regs_out_i;

            when zpx2 =>

               zw_b1 <= d_alu_i;

            when ab1 =>

               zw_b5 <= d_i;

               zw_b11 <= d_regs_out_i;

            when ab2 =>

               zw_b6 <= d_i;

            when absx1 =>

               zw_b5 <= d_i;

               zw_b11 <= d_regs_out_i;

            when absx2 =>

               zw_b6 <= d_i;

               zw_b1 <= d_alu_i;

               zw_reg_0flag <= reg_0flag_i;

            when absx3 =>

               zw_b3 <= d_alu_i;

            when ind1 =>

               zw_b5 <= d_i;

               zw_b11 <= d_regs_out_i;

            when ind3 =>

               zw_b5 <= d_i;

            when ind2 =>

               zw_b1 <= d_alu_i;

               zw_b6 <= d_i;

            when indy1 =>

               zw_b5 <= d_i;

               zw_b11 <= d_regs_out_i;

            when indy2 =>

               zw_b2 <= d_i;

               zw_b1 <= d_alu_i;

            when indy3 =>

               zw_b5 <= d_i;

               zw_b6 <= d_alu_i;

               zw_reg_0flag <= reg_0flag_i;

            when indy4 =>

               zw_b3 <= d_alu_i;

            when indx1 =>

               zw_b5 <= d_i;

               zw_b11 <= d_regs_out_i;

            when indx4 =>

               zw_b2 <= d_i;

            when indx2 =>