OpenCores
URL https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk

Subversion Repositories cpu_lecture

[/] [cpu_lecture/] [trunk/] [html/] [10_Listing_of_alu_vhd.html] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jsauermann
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"
2
"http://www.w3.org/TR/html4/strict.dtd">
3
<HTML>
4
<HEAD>
5
<TITLE>html/Listing_of_alu_vhd</TITLE>
6
<META NAME="generator" CONTENT="HTML::TextToHTML v2.46">
7
<LINK REL="stylesheet" TYPE="text/css" HREF="lecture.css">
8
</HEAD>
9
<BODY>
10
<P><table class="ttop"><th class="tpre"><a href="09_Toolchain_Setup.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="11_Listing_of_avr_fpga.vhd.html">Next Lesson</a></th></table>
11
<hr>
12
 
13
<H1><A NAME="section_1">10 LISTING OF alu.vhd</A></H1>
14
 
15
<pre class="vhdl">
16
 
17
  1     -------------------------------------------------------------------------------
18
  2     --
19
  3     -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
20
  4     --
21
  5     --  This code is free software: you can redistribute it and/or modify
22
  6     --  it under the terms of the GNU General Public License as published by
23
  7     --  the Free Software Foundation, either version 3 of the License, or
24
  8     --  (at your option) any later version.
25
  9     --
26
 10     --  This code is distributed in the hope that it will be useful,
27
 11     --  but WITHOUT ANY WARRANTY; without even the implied warranty of
28
 12     --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
29
 13     --  GNU General Public License for more details.
30
 14     --
31
 15     --  You should have received a copy of the GNU General Public License
32
 16     --  along with this code (see the file named COPYING).
33
 17     --  If not, see http://www.gnu.org/licenses/.
34
 18     --
35
 19     -------------------------------------------------------------------------------
36
 20     -------------------------------------------------------------------------------
37
 21     --
38
 22     -- Module Name:    alu - Behavioral
39
 23     -- Create Date:    13:51:24 11/07/2009
40
 24     -- Description:    arithmetic logic unit of a CPU
41
 25     --
42
 26     -------------------------------------------------------------------------------
43
 27     --
44
 28     library IEEE;
45
 29     use IEEE.std_logic_1164.ALL;
46
 30     use IEEE.std_logic_ARITH.ALL;
47
 31     use IEEE.std_logic_UNSIGNED.ALL;
48
 32
49
 33     use work.common.ALL;
50
 34
51
 35     entity alu is
52
 36         port (  I_ALU_OP    : in  std_logic_vector( 4 downto 0);
53
 37                 I_BIT       : in  std_logic_vector( 3 downto 0);
54
 38                 I_D         : in  std_logic_vector(15 downto 0);
55
 39                 I_D0        : in  std_logic;
56
 40                 I_DIN       : in  std_logic_vector( 7 downto 0);
57
 41                 I_FLAGS     : in  std_logic_vector( 7 downto 0);
58
 42                 I_IMM       : in  std_logic_vector( 7 downto 0);
59
 43                 I_PC        : in  std_logic_vector(15 downto 0);
60
 44                 I_R         : in  std_logic_vector(15 downto 0);
61
 45                 I_R0        : in  std_logic;
62
 46                 I_RSEL      : in  std_logic_vector( 1 downto 0);
63
 47
64
 48                 Q_FLAGS     : out std_logic_vector( 9 downto 0);
65
 49                 Q_DOUT      : out std_logic_vector(15 downto 0));
66
 50     end alu;
67
 51
68
 52     architecture Behavioral of alu is
69
 53
70
 54     function ze(A: std_logic_vector(7 downto 0)) return std_logic is
71
 55     begin
72
 56         return not (A(0) or A(1) or A(2) or A(3) or
73
 57                     A(4) or A(5) or A(6) or A(7));
74
 58     end;
75
 59
76
 60     function cy(D, R, S: std_logic) return std_logic is
77
 61     begin
78
 62         return (D and R) or (D and not S) or (R and not S);
79
 63     end;
80
 64
81
 65     function ov(D, R, S: std_logic) return std_logic is
82
 66     begin
83
 67         return (D and R and (not S)) or ((not D) and (not R) and S);
84
 68     end;
85
 69
86
 70     function si(D, R, S: std_logic) return std_logic is
87
 71     begin
88
 72         return S xor ov(D, R, S);
89
 73     end;
90
 74
91
 75     signal L_ADC_DR     : std_logic_vector( 7 downto 0);    -- D + R + Carry
92
 76     signal L_ADD_DR     : std_logic_vector( 7 downto 0);    -- D + R
93
 77     signal L_ADIW_D     : std_logic_vector(15 downto 0);    -- D + IMM
94
 78     signal L_AND_DR     : std_logic_vector( 7 downto 0);    -- D and R
95
 79     signal L_ASR_D      : std_logic_vector( 7 downto 0);    -- (signed D) >> 1
96
 80     signal L_D8         : std_logic_vector( 7 downto 0);    -- D(7 downto 0)
97
 81     signal L_DEC_D      : std_logic_vector( 7 downto 0);    -- D - 1
98
 82     signal L_DOUT       : std_logic_vector(15 downto 0);
99
 83     signal L_INC_D      : std_logic_vector( 7 downto 0);    -- D + 1
100
 84     signal L_LSR_D      : std_logic_vector( 7 downto 0);    -- (unsigned) D >> 1
101
 85     signal L_MASK_I     : std_logic_vector( 7 downto 0);    -- 1 << IMM
102
 86     signal L_NEG_D      : std_logic_vector( 7 downto 0);    -- 0 - D
103
 87     signal L_NOT_D      : std_logic_vector( 7 downto 0);    -- 0 not D
104
 88     signal L_OR_DR      : std_logic_vector( 7 downto 0);    -- D or R
105
 89     signal L_PROD       : std_logic_vector(17 downto 0);    -- D * R
106
 90     signal L_R8         : std_logic_vector( 7 downto 0);    -- odd or even R
107
 91     signal L_RI8        : std_logic_vector( 7 downto 0);    -- R8 or IMM
108
 92     signal L_RBIT       : std_logic;
109
 93     signal L_SBIW_D     : std_logic_vector(15 downto 0);    -- D - IMM
110
 94     signal L_ROR_D      : std_logic_vector( 7 downto 0);    -- D rotated right
111
 95     signal L_SBC_DR     : std_logic_vector( 7 downto 0);    -- D - R - Carry
112
 96     signal L_SIGN_D     : std_logic;
113
 97     signal L_SIGN_R     : std_logic;
114
 98     signal L_SUB_DR     : std_logic_vector( 7 downto 0);    -- D - R
115
 99     signal L_SWAP_D     : std_logic_vector( 7 downto 0);    -- D swapped
116
100     signal L_XOR_DR     : std_logic_vector( 7 downto 0);    -- D xor R
117
101
118
102     begin
119
103
120
104         dinbit: process(I_DIN, I_BIT(2 downto 0))
121
105         begin
122
106             case I_BIT(2 downto 0) is
123
107                 when "000"  => L_RBIT <= I_DIN(0);   L_MASK_I <= "00000001";
124
108                 when "001"  => L_RBIT <= I_DIN(1);   L_MASK_I <= "00000010";
125
109                 when "010"  => L_RBIT <= I_DIN(2);   L_MASK_I <= "00000100";
126
110                 when "011"  => L_RBIT <= I_DIN(3);   L_MASK_I <= "00001000";
127
111                 when "100"  => L_RBIT <= I_DIN(4);   L_MASK_I <= "00010000";
128
112                 when "101"  => L_RBIT <= I_DIN(5);   L_MASK_I <= "00100000";
129
113                 when "110"  => L_RBIT <= I_DIN(6);   L_MASK_I <= "01000000";
130
114                 when others => L_RBIT <= I_DIN(7);   L_MASK_I <= "10000000";
131
115             end case;
132
116         end process;
133
117
134
118         process(L_ADC_DR, L_ADD_DR, L_ADIW_D, I_ALU_OP, L_AND_DR, L_ASR_D,
135
119                 I_BIT, I_D, L_D8, L_DEC_D, I_DIN, I_FLAGS, I_IMM, L_MASK_I,
136
120                 L_INC_D, L_LSR_D, L_NEG_D, L_NOT_D, L_OR_DR, I_PC, L_PROD,
137
121                 I_R, L_RI8, L_RBIT, L_ROR_D, L_SBIW_D, L_SUB_DR, L_SBC_DR,
138
122                 L_SIGN_D, L_SIGN_R, L_SWAP_D, L_XOR_DR)
139
123         begin
140
124             Q_FLAGS <= "00" & I_FLAGS;
141
125             L_DOUT <= X"0000";
142
126
143
127             case I_ALU_OP is
144
128                 when ALU_ADC =>
145
129                     L_DOUT <= L_ADC_DR & L_ADC_DR;
146
130                     Q_FLAGS(0) <= cy(L_D8(7), L_RI8(7), L_ADC_DR(7));   -- Carry
147
131                     Q_FLAGS(1) <= ze(L_ADC_DR);                         -- Zero
148
132                     Q_FLAGS(2) <= L_ADC_DR(7);                          -- Negative
149
133                     Q_FLAGS(3) <= ov(L_D8(7), L_RI8(7), L_ADC_DR(7));   -- Overflow
150
134                     Q_FLAGS(4) <= si(L_D8(7), L_RI8(7), L_ADC_DR(7));   -- Signed
151
135                     Q_FLAGS(5) <= cy(L_D8(3), L_RI8(3), L_ADC_DR(3));   -- Halfcarry
152
136
153
137                 when ALU_ADD =>
154
138                     L_DOUT <= L_ADD_DR & L_ADD_DR;
155
139                     Q_FLAGS(0) <= cy(L_D8(7), L_RI8(7), L_ADD_DR(7));   -- Carry
156
140                     Q_FLAGS(1) <= ze(L_ADD_DR);                         -- Zero
157
141                     Q_FLAGS(2) <= L_ADD_DR(7);                          -- Negative
158
142                     Q_FLAGS(3) <= ov(L_D8(7), L_RI8(7), L_ADD_DR(7));   -- Overflow
159
143                     Q_FLAGS(4) <= si(L_D8(7), L_RI8(7), L_ADD_DR(7));   -- Signed
160
144                     Q_FLAGS(5) <= cy(L_D8(3), L_RI8(3), L_ADD_DR(3));   -- Halfcarry
161
145
162
146                 when ALU_ADIW =>
163
147                     L_DOUT <= L_ADIW_D;
164
148                     Q_FLAGS(0) <= L_ADIW_D(15) and not I_D(15);         -- Carry
165
149                     Q_FLAGS(1) <= ze(L_ADIW_D(15 downto 8)) and
166
150                                   ze(L_ADIW_D(7 downto 0));             -- Zero
167
151                     Q_FLAGS(2) <= L_ADIW_D(15);                         -- Negative
168
152                     Q_FLAGS(3) <= I_D(15) and not L_ADIW_D(15);         -- Overflow
169
153                     Q_FLAGS(4) <= (L_ADIW_D(15) and not I_D(15))
170
154                               xor (I_D(15) and not L_ADIW_D(15));       -- Signed
171
155
172
156                 when ALU_AND =>
173
157                     L_DOUT <= L_AND_DR & L_AND_DR;
174
158                     Q_FLAGS(1) <= ze(L_AND_DR);                         -- Zero
175
159                     Q_FLAGS(2) <= L_AND_DR(7);                          -- Negative
176
160                     Q_FLAGS(3) <= '0';                                  -- Overflow
177
161                     Q_FLAGS(4) <= L_AND_DR(7);                          -- Signed
178
162
179
163                 when ALU_ASR =>
180
164                     L_DOUT <= L_ASR_D & L_ASR_D;
181
165                     Q_FLAGS(0) <= L_D8(0);                              -- Carry
182
166                     Q_FLAGS(1) <= ze(L_ASR_D);                          -- Zero
183
167                     Q_FLAGS(2) <= L_D8(7);                              -- Negative
184
168                     Q_FLAGS(3) <= L_D8(0) xor L_D8(7);                  -- Overflow
185
169                     Q_FLAGS(4) <= L_D8(0);                              -- Signed
186
170
187
171                 when ALU_BLD =>     -- copy T flag to DOUT
188
172                     case I_BIT(2 downto 0) is
189
173                         when "000"  => L_DOUT( 0) <= I_FLAGS(6);
190
174                                        L_DOUT( 8) <= I_FLAGS(6);
191
175                         when "001"  => L_DOUT( 1) <= I_FLAGS(6);
192
176                                        L_DOUT( 9) <= I_FLAGS(6);
193
177                         when "010"  => L_DOUT( 2) <= I_FLAGS(6);
194
178                                        L_DOUT(10) <= I_FLAGS(6);
195
179                         when "011"  => L_DOUT( 3) <= I_FLAGS(6);
196
180                                        L_DOUT(11) <= I_FLAGS(6);
197
181                         when "100"  => L_DOUT( 4) <= I_FLAGS(6);
198
182                                        L_DOUT(12) <= I_FLAGS(6);
199
183                         when "101"  => L_DOUT( 5) <= I_FLAGS(6);
200
184                                        L_DOUT(13) <= I_FLAGS(6);
201
185                         when "110"  => L_DOUT( 6) <= I_FLAGS(6);
202
186                                        L_DOUT(14) <= I_FLAGS(6);
203
187                         when others => L_DOUT( 7) <= I_FLAGS(6);
204
188                                        L_DOUT(15) <= I_FLAGS(6);
205
189                     end case;
206
190
207
191                 when ALU_BIT_CS =>  -- copy I_DIN to T flag
208
192                     Q_FLAGS(6) <= L_RBIT xor not I_BIT(3);
209
193                     Q_FLAGS(9) <= L_RBIT xor not I_BIT(3);
210
194                     if (I_BIT(3) = '0') then    -- clear
211
195                         L_DOUT(15 downto 8) <= I_DIN and not L_MASK_I;
212
196                         L_DOUT( 7 downto 0) <= I_DIN and not L_MASK_I;
213
197                     else                        -- set
214
198                         L_DOUT(15 downto 8) <= I_DIN or L_MASK_I;
215
199                         L_DOUT( 7 downto 0) <= I_DIN or L_MASK_I;
216
200                     end if;
217
201
218
202                 when ALU_COM =>
219
203                     L_DOUT <= L_NOT_D & L_NOT_D;
220
204                     Q_FLAGS(0) <= '1';                                  -- Carry
221
205                     Q_FLAGS(1) <= ze(not L_D8);                         -- Zero
222
206                     Q_FLAGS(2) <= not L_D8(7);                          -- Negative
223
207                     Q_FLAGS(3) <= '0';                                  -- Overflow
224
208                     Q_FLAGS(4) <= not L_D8(7);                          -- Signed
225
209
226
210                 when ALU_DEC =>
227
211                     L_DOUT <= L_DEC_D & L_DEC_D;
228
212                     Q_FLAGS(1) <= ze(L_DEC_D);                          -- Zero
229
213                     Q_FLAGS(2) <= L_DEC_D(7);                           -- Negative
230
214                     if (L_D8 = X"80") then
231
215                         Q_FLAGS(3) <= '1';                              -- Overflow
232
216                         Q_FLAGS(4) <= not L_DEC_D(7);                   -- Signed
233
217                     else
234
218                         Q_FLAGS(3) <= '0';                              -- Overflow
235
219                         Q_FLAGS(4) <= L_DEC_D(7);                       -- Signed
236
220                     end if;
237
221
238
222                 when ALU_EOR =>
239
223                     L_DOUT <= L_XOR_DR & L_XOR_DR;
240
224                     Q_FLAGS(1) <= ze(L_XOR_DR);                         -- Zero
241
225                     Q_FLAGS(2) <= L_XOR_DR(7);                          -- Negative
242
226                     Q_FLAGS(3) <= '0';                                  -- Overflow
243
227                     Q_FLAGS(4) <= L_XOR_DR(7);                          -- Signed
244
228
245
229                 when ALU_INC =>
246
230                     L_DOUT <= L_INC_D & L_INC_D;
247
231                     Q_FLAGS(1) <= ze(L_INC_D);                          -- Zero
248
232                     Q_FLAGS(2) <= L_INC_D(7);                           -- Negative
249
233                     if (L_D8 = X"7F") then
250
234                         Q_FLAGS(3) <= '1';                              -- Overflow
251
235                         Q_FLAGS(4) <= not L_INC_D(7);                   -- Signed
252
236                     else
253
237                         Q_FLAGS(3) <= '0';                              -- Overflow
254
238                         Q_FLAGS(4) <= L_INC_D(7);                       -- Signed
255
239                     end if;
256
240
257
241                 when ALU_INTR =>
258
242                     L_DOUT <= I_PC;
259
243                     Q_FLAGS(7) <= I_IMM(6);    -- ena/disable interrupts
260
244
261
245                 when ALU_LSR  =>
262
246                     L_DOUT <= L_LSR_D & L_LSR_D;
263
247                     Q_FLAGS(0) <= L_D8(0);                              -- Carry
264
248                     Q_FLAGS(1) <= ze(L_LSR_D);                          -- Zero
265
249                     Q_FLAGS(2) <= '0';                                  -- Negative
266
250                     Q_FLAGS(3) <= L_D8(0);                              -- Overflow
267
251                     Q_FLAGS(4) <= L_D8(0);                              -- Signed
268
252
269
253                 when ALU_D_MV_Q =>
270
254                     L_DOUT <= L_D8 & L_D8;
271
255
272
256                 when ALU_R_MV_Q =>
273
257                     L_DOUT <= L_RI8 & L_RI8;
274
258
275
259                 when ALU_MV_16 =>
276
260                     L_DOUT <= I_R(15 downto 8) & L_RI8;
277
261
278
262                 when ALU_MULT =>
279
263                     Q_FLAGS(0) <= L_PROD(15);                           -- Carry
280
264                     if I_IMM(7) = '0' then              -- MUL
281
265                         L_DOUT <= L_PROD(15 downto 0);
282
266                         Q_FLAGS(1) <= ze(L_PROD(15 downto 8))           -- Zero
283
267                                 and ze(L_PROD( 7 downto 0));
284
268                     else                                -- FMUL
285
269                         L_DOUT <= L_PROD(14 downto 0) & "0";
286
270                         Q_FLAGS(1) <= ze(L_PROD(14 downto 7))           -- Zero
287
271                                 and ze(L_PROD( 6 downto 0) & "0");
288
272                     end if;
289
273
290
274                 when ALU_NEG =>
291
275                     L_DOUT <= L_NEG_D & L_NEG_D;
292
276                     Q_FLAGS(0) <= not ze(L_D8);                         -- Carry
293
277                     Q_FLAGS(1) <= ze(L_NEG_D);                          -- Zero
294
278                     Q_FLAGS(2) <= L_NEG_D(7);                           -- Negative
295
279                     if (L_D8 = X"80") then
296
280                         Q_FLAGS(3) <= '1';                              -- Overflow
297
281                         Q_FLAGS(4) <= not L_NEG_D(7);                   -- Signed
298
282                     else
299
283                         Q_FLAGS(3) <= '0';                              -- Overflow
300
284                         Q_FLAGS(4) <= L_NEG_D(7);                       -- Signed
301
285                     end if;
302
286                     Q_FLAGS(5) <= L_D8(3) or L_NEG_D(3);                -- Halfcarry
303
287
304
288                 when ALU_OR =>
305
289                     L_DOUT <= L_OR_DR & L_OR_DR;
306
290                     Q_FLAGS(1) <= ze(L_OR_DR);                          -- Zero
307
291                     Q_FLAGS(2) <= L_OR_DR(7);                           -- Negative
308
292                     Q_FLAGS(3) <= '0';                                  -- Overflow
309
293                     Q_FLAGS(4) <= L_OR_DR(7);                           -- Signed
310
294
311
295                 when ALU_PC_1 =>    -- ICALL, RCALL
312
296                     L_DOUT <= I_PC + X"0001";
313
297
314
298                 when ALU_PC_2 =>    -- CALL
315
299                     L_DOUT <= I_PC + X"0002";
316
300
317
301                 when ALU_ROR =>
318
302                     L_DOUT <= L_ROR_D & L_ROR_D;
319
303                     Q_FLAGS(1) <= ze(L_ROR_D);                          -- Zero
320
304                     Q_FLAGS(2) <= I_FLAGS(0);                           -- Negative
321
305                     Q_FLAGS(3) <= I_FLAGS(0) xor L_D8(0);               -- Overflow
322
306                     Q_FLAGS(4) <= I_FLAGS(0);                           -- Signed
323
307
324
308                 when ALU_SBC =>
325
309                     L_DOUT <= L_SBC_DR & L_SBC_DR;
326
310                     Q_FLAGS(0) <= cy(L_SBC_DR(7), L_RI8(7), L_D8(7));   -- Carry
327
311                     Q_FLAGS(1) <= ze(L_SBC_DR) and I_FLAGS(1);          -- Zero
328
312                     Q_FLAGS(2) <= L_SBC_DR(7);                          -- Negative
329
313                     Q_FLAGS(3) <= ov(L_SBC_DR(7), L_RI8(7), L_D8(7));   -- Overflow
330
314                     Q_FLAGS(4) <= si(L_SBC_DR(7), L_RI8(7), L_D8(7));   -- Signed
331
315                     Q_FLAGS(5) <= cy(L_SBC_DR(3), L_RI8(3), L_D8(3));   -- Halfcarry
332
316
333
317                 when ALU_SBIW =>
334
318                     L_DOUT <= L_SBIW_D;
335
319                     Q_FLAGS(0) <= L_SBIW_D(15) and not I_D(15);         -- Carry
336
320                     Q_FLAGS(1) <= ze(L_SBIW_D(15 downto 8)) and
337
321                                   ze(L_SBIW_D(7 downto 0));             -- Zero
338
322                     Q_FLAGS(2) <= L_SBIW_D(15);                         -- Negative
339
323                     Q_FLAGS(3) <= I_D(15) and not L_SBIW_D(15);         -- Overflow
340
324                     Q_FLAGS(4) <=  (L_SBIW_D(15) and not I_D(15))
341
325                                xor (I_D(15) and not L_SBIW_D(15));      -- Signed
342
326
343
327                 when ALU_SREG =>
344
328                     case I_BIT(2 downto 0) is
345
329                         when "000"  => Q_FLAGS(0) <= I_BIT(3);
346
330                         when "001"  => Q_FLAGS(1) <= I_BIT(3);
347
331                         when "010"  => Q_FLAGS(2) <= I_BIT(3);
348
332                         when "011"  => Q_FLAGS(3) <= I_BIT(3);
349
333                         when "100"  => Q_FLAGS(4) <= I_BIT(3);
350
334                         when "101"  => Q_FLAGS(5) <= I_BIT(3);
351
335                         when "110"  => Q_FLAGS(6) <= I_BIT(3);
352
336                         when others => Q_FLAGS(7) <= I_BIT(3);
353
337                     end case;
354
338
355
339                 when ALU_SUB =>
356
340                     L_DOUT <= L_SUB_DR & L_SUB_DR;
357
341                     Q_FLAGS(0) <= cy(L_SUB_DR(7), L_RI8(7), L_D8(7));   -- Carry
358
342                     Q_FLAGS(1) <= ze(L_SUB_DR);                         -- Zero
359
343                     Q_FLAGS(2) <= L_SUB_DR(7);                          -- Negative
360
344                     Q_FLAGS(3) <= ov(L_SUB_DR(7), L_RI8(7), L_D8(7));   -- Overflow
361
345                     Q_FLAGS(4) <= si(L_SUB_DR(7), L_RI8(7), L_D8(7));   -- Signed
362
346                     Q_FLAGS(5) <= cy(L_SUB_DR(3), L_RI8(3), L_D8(3));   -- Halfcarry
363
347                     Q_FLAGS(8) <= ze(L_SUB_DR);                         -- temp Zero
364
348
365
349                 when ALU_SWAP =>
366
350                     L_DOUT <= L_SWAP_D & L_SWAP_D;
367
351
368
352                 when others =>
369
353             end case;
370
354         end Process;
371
355
372
356         L_D8 <= I_D(15 downto 8) when (I_D0 = '1') else I_D(7 downto 0);
373
357         L_R8 <= I_R(15 downto 8) when (I_R0 = '1') else I_R(7 downto 0);
374
358         L_RI8 <= I_IMM           when (I_RSEL = RS_IMM) else L_R8;
375
359
376
360         L_ADIW_D  <= I_D + ("0000000000" & I_IMM(5 downto 0));
377
361         L_SBIW_D  <= I_D - ("0000000000" & I_IMM(5 downto 0));
378
362         L_ADD_DR  <= L_D8 + L_RI8;
379
363         L_ADC_DR  <= L_ADD_DR + ("0000000" & I_FLAGS(0));
380
364         L_ASR_D   <= L_D8(7) & L_D8(7 downto 1);
381
365         L_AND_DR  <= L_D8 and L_RI8;
382
366         L_DEC_D   <= L_D8 - X"01";
383
367         L_INC_D   <= L_D8 + X"01";
384
368         L_LSR_D   <= '0' & L_D8(7 downto 1);
385
369         L_NEG_D   <= X"00" - L_D8;
386
370         L_NOT_D   <= not L_D8;
387
371         L_OR_DR   <= L_D8 or L_RI8;
388
372         L_PROD    <= (L_SIGN_D & L_D8) * (L_SIGN_R & L_R8);
389
373         L_ROR_D   <= I_FLAGS(0) &  L_D8(7 downto 1);
390
374         L_SUB_DR  <= L_D8 - L_RI8;
391
375         L_SBC_DR  <= L_SUB_DR - ("0000000" & I_FLAGS(0));
392
376         L_SIGN_D  <= L_D8(7) and I_IMM(6);
393
377         L_SIGN_R  <= L_R8(7) and I_IMM(5);
394
378         L_SWAP_D  <= L_D8(3 downto 0) & L_D8(7 downto 4);
395
379         L_XOR_DR  <= L_D8 xor L_R8;
396
380
397
381         Q_DOUT <= (I_DIN & I_DIN) when (I_RSEL = RS_DIN) else L_DOUT;
398
382
399
383     end Behavioral;
400
384
401
<pre class="filename">
402
src/alu.vhd
403
</pre></pre>
404
<P>
405
 
406
<P><hr><BR>
407
<table class="ttop"><th class="tpre"><a href="09_Toolchain_Setup.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="11_Listing_of_avr_fpga.vhd.html">Next Lesson</a></th></table>
408
</BODY>
409
</HTML>

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.