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<P><table class="ttop"><th class="tpre"><a href="09_Toolchain_Setup.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="11_Listing_of_avr_fpga.vhd.html">Next Lesson</a></th></table>
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<hr>
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<H1><A NAME="section_1">10 LISTING OF alu.vhd</A></H1>
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<pre class="vhdl">
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1 -------------------------------------------------------------------------------
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2 --
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3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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4 --
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5 -- This code is free software: you can redistribute it and/or modify
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6 -- it under the terms of the GNU General Public License as published by
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7 -- the Free Software Foundation, either version 3 of the License, or
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8 -- (at your option) any later version.
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9 --
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10 -- This code is distributed in the hope that it will be useful,
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11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 -- GNU General Public License for more details.
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14 --
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15 -- You should have received a copy of the GNU General Public License
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16 -- along with this code (see the file named COPYING).
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17 -- If not, see http://www.gnu.org/licenses/.
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18 --
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19 -------------------------------------------------------------------------------
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20 -------------------------------------------------------------------------------
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21 --
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22 -- Module Name: alu - Behavioral
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23 -- Create Date: 13:51:24 11/07/2009
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24 -- Description: arithmetic logic unit of a CPU
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25 --
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26 -------------------------------------------------------------------------------
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27 --
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28 library IEEE;
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29 use IEEE.std_logic_1164.ALL;
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30 use IEEE.std_logic_ARITH.ALL;
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31 use IEEE.std_logic_UNSIGNED.ALL;
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32
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33 use work.common.ALL;
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34
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35 entity alu is
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36 port ( I_ALU_OP : in std_logic_vector( 4 downto 0);
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37 I_BIT : in std_logic_vector( 3 downto 0);
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38 I_D : in std_logic_vector(15 downto 0);
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39 I_D0 : in std_logic;
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40 I_DIN : in std_logic_vector( 7 downto 0);
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41 I_FLAGS : in std_logic_vector( 7 downto 0);
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42 I_IMM : in std_logic_vector( 7 downto 0);
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43 I_PC : in std_logic_vector(15 downto 0);
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44 I_R : in std_logic_vector(15 downto 0);
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45 I_R0 : in std_logic;
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46 I_RSEL : in std_logic_vector( 1 downto 0);
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47
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48 Q_FLAGS : out std_logic_vector( 9 downto 0);
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49 Q_DOUT : out std_logic_vector(15 downto 0));
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50 end alu;
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51
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52 architecture Behavioral of alu is
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53
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54 function ze(A: std_logic_vector(7 downto 0)) return std_logic is
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55 begin
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56 return not (A(0) or A(1) or A(2) or A(3) or
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57 A(4) or A(5) or A(6) or A(7));
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58 end;
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59
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60 function cy(D, R, S: std_logic) return std_logic is
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61 begin
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62 return (D and R) or (D and not S) or (R and not S);
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63 end;
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64
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65 function ov(D, R, S: std_logic) return std_logic is
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66 begin
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67 return (D and R and (not S)) or ((not D) and (not R) and S);
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68 end;
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69
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70 function si(D, R, S: std_logic) return std_logic is
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71 begin
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72 return S xor ov(D, R, S);
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73 end;
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74
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75 signal L_ADC_DR : std_logic_vector( 7 downto 0); -- D + R + Carry
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76 signal L_ADD_DR : std_logic_vector( 7 downto 0); -- D + R
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77 signal L_ADIW_D : std_logic_vector(15 downto 0); -- D + IMM
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78 signal L_AND_DR : std_logic_vector( 7 downto 0); -- D and R
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79 signal L_ASR_D : std_logic_vector( 7 downto 0); -- (signed D) >> 1
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80 signal L_D8 : std_logic_vector( 7 downto 0); -- D(7 downto 0)
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81 signal L_DEC_D : std_logic_vector( 7 downto 0); -- D - 1
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82 signal L_DOUT : std_logic_vector(15 downto 0);
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83 signal L_INC_D : std_logic_vector( 7 downto 0); -- D + 1
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84 signal L_LSR_D : std_logic_vector( 7 downto 0); -- (unsigned) D >> 1
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85 signal L_MASK_I : std_logic_vector( 7 downto 0); -- 1 << IMM
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86 signal L_NEG_D : std_logic_vector( 7 downto 0); -- 0 - D
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87 signal L_NOT_D : std_logic_vector( 7 downto 0); -- 0 not D
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88 signal L_OR_DR : std_logic_vector( 7 downto 0); -- D or R
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89 signal L_PROD : std_logic_vector(17 downto 0); -- D * R
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90 signal L_R8 : std_logic_vector( 7 downto 0); -- odd or even R
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91 signal L_RI8 : std_logic_vector( 7 downto 0); -- R8 or IMM
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92 signal L_RBIT : std_logic;
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93 signal L_SBIW_D : std_logic_vector(15 downto 0); -- D - IMM
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94 signal L_ROR_D : std_logic_vector( 7 downto 0); -- D rotated right
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95 signal L_SBC_DR : std_logic_vector( 7 downto 0); -- D - R - Carry
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96 signal L_SIGN_D : std_logic;
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97 signal L_SIGN_R : std_logic;
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98 signal L_SUB_DR : std_logic_vector( 7 downto 0); -- D - R
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99 signal L_SWAP_D : std_logic_vector( 7 downto 0); -- D swapped
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100 signal L_XOR_DR : std_logic_vector( 7 downto 0); -- D xor R
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101
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102 begin
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103
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104 dinbit: process(I_DIN, I_BIT(2 downto 0))
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105 begin
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106 case I_BIT(2 downto 0) is
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107 when "000" => L_RBIT <= I_DIN(0); L_MASK_I <= "00000001";
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108 when "001" => L_RBIT <= I_DIN(1); L_MASK_I <= "00000010";
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109 when "010" => L_RBIT <= I_DIN(2); L_MASK_I <= "00000100";
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110 when "011" => L_RBIT <= I_DIN(3); L_MASK_I <= "00001000";
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111 when "100" => L_RBIT <= I_DIN(4); L_MASK_I <= "00010000";
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112 when "101" => L_RBIT <= I_DIN(5); L_MASK_I <= "00100000";
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113 when "110" => L_RBIT <= I_DIN(6); L_MASK_I <= "01000000";
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114 when others => L_RBIT <= I_DIN(7); L_MASK_I <= "10000000";
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115 end case;
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116 end process;
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117
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118 process(L_ADC_DR, L_ADD_DR, L_ADIW_D, I_ALU_OP, L_AND_DR, L_ASR_D,
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119 I_BIT, I_D, L_D8, L_DEC_D, I_DIN, I_FLAGS, I_IMM, L_MASK_I,
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120 L_INC_D, L_LSR_D, L_NEG_D, L_NOT_D, L_OR_DR, I_PC, L_PROD,
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121 I_R, L_RI8, L_RBIT, L_ROR_D, L_SBIW_D, L_SUB_DR, L_SBC_DR,
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122 L_SIGN_D, L_SIGN_R, L_SWAP_D, L_XOR_DR)
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123 begin
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124 Q_FLAGS <= "00" & I_FLAGS;
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125 L_DOUT <= X"0000";
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126
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127 case I_ALU_OP is
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128 when ALU_ADC =>
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129 L_DOUT <= L_ADC_DR & L_ADC_DR;
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130 Q_FLAGS(0) <= cy(L_D8(7), L_RI8(7), L_ADC_DR(7)); -- Carry
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131 Q_FLAGS(1) <= ze(L_ADC_DR); -- Zero
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132 Q_FLAGS(2) <= L_ADC_DR(7); -- Negative
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133 Q_FLAGS(3) <= ov(L_D8(7), L_RI8(7), L_ADC_DR(7)); -- Overflow
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134 Q_FLAGS(4) <= si(L_D8(7), L_RI8(7), L_ADC_DR(7)); -- Signed
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135 Q_FLAGS(5) <= cy(L_D8(3), L_RI8(3), L_ADC_DR(3)); -- Halfcarry
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136
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137 when ALU_ADD =>
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138 L_DOUT <= L_ADD_DR & L_ADD_DR;
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139 Q_FLAGS(0) <= cy(L_D8(7), L_RI8(7), L_ADD_DR(7)); -- Carry
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140 Q_FLAGS(1) <= ze(L_ADD_DR); -- Zero
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141 Q_FLAGS(2) <= L_ADD_DR(7); -- Negative
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142 Q_FLAGS(3) <= ov(L_D8(7), L_RI8(7), L_ADD_DR(7)); -- Overflow
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143 Q_FLAGS(4) <= si(L_D8(7), L_RI8(7), L_ADD_DR(7)); -- Signed
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144 Q_FLAGS(5) <= cy(L_D8(3), L_RI8(3), L_ADD_DR(3)); -- Halfcarry
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145
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146 when ALU_ADIW =>
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147 L_DOUT <= L_ADIW_D;
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148 Q_FLAGS(0) <= L_ADIW_D(15) and not I_D(15); -- Carry
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149 Q_FLAGS(1) <= ze(L_ADIW_D(15 downto 8)) and
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150 ze(L_ADIW_D(7 downto 0)); -- Zero
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151 Q_FLAGS(2) <= L_ADIW_D(15); -- Negative
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152 Q_FLAGS(3) <= I_D(15) and not L_ADIW_D(15); -- Overflow
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153 Q_FLAGS(4) <= (L_ADIW_D(15) and not I_D(15))
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154 xor (I_D(15) and not L_ADIW_D(15)); -- Signed
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155
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156 when ALU_AND =>
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157 L_DOUT <= L_AND_DR & L_AND_DR;
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158 Q_FLAGS(1) <= ze(L_AND_DR); -- Zero
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159 Q_FLAGS(2) <= L_AND_DR(7); -- Negative
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160 Q_FLAGS(3) <= '0'; -- Overflow
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161 Q_FLAGS(4) <= L_AND_DR(7); -- Signed
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162
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163 when ALU_ASR =>
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164 L_DOUT <= L_ASR_D & L_ASR_D;
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165 Q_FLAGS(0) <= L_D8(0); -- Carry
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166 Q_FLAGS(1) <= ze(L_ASR_D); -- Zero
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167 Q_FLAGS(2) <= L_D8(7); -- Negative
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168 Q_FLAGS(3) <= L_D8(0) xor L_D8(7); -- Overflow
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169 Q_FLAGS(4) <= L_D8(0); -- Signed
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170
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171 when ALU_BLD => -- copy T flag to DOUT
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172 case I_BIT(2 downto 0) is
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173 when "000" => L_DOUT( 0) <= I_FLAGS(6);
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174 L_DOUT( 8) <= I_FLAGS(6);
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175 when "001" => L_DOUT( 1) <= I_FLAGS(6);
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176 L_DOUT( 9) <= I_FLAGS(6);
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177 when "010" => L_DOUT( 2) <= I_FLAGS(6);
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178 L_DOUT(10) <= I_FLAGS(6);
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179 when "011" => L_DOUT( 3) <= I_FLAGS(6);
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180 L_DOUT(11) <= I_FLAGS(6);
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181 when "100" => L_DOUT( 4) <= I_FLAGS(6);
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182 L_DOUT(12) <= I_FLAGS(6);
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183 when "101" => L_DOUT( 5) <= I_FLAGS(6);
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184 L_DOUT(13) <= I_FLAGS(6);
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185 when "110" => L_DOUT( 6) <= I_FLAGS(6);
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186 L_DOUT(14) <= I_FLAGS(6);
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187 when others => L_DOUT( 7) <= I_FLAGS(6);
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188 L_DOUT(15) <= I_FLAGS(6);
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189 end case;
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190
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191 when ALU_BIT_CS => -- copy I_DIN to T flag
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192 Q_FLAGS(6) <= L_RBIT xor not I_BIT(3);
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193 Q_FLAGS(9) <= L_RBIT xor not I_BIT(3);
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194 if (I_BIT(3) = '0') then -- clear
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195 L_DOUT(15 downto 8) <= I_DIN and not L_MASK_I;
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196 L_DOUT( 7 downto 0) <= I_DIN and not L_MASK_I;
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197 else -- set
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198 L_DOUT(15 downto 8) <= I_DIN or L_MASK_I;
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199 L_DOUT( 7 downto 0) <= I_DIN or L_MASK_I;
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200 end if;
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201
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202 when ALU_COM =>
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203 L_DOUT <= L_NOT_D & L_NOT_D;
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204 Q_FLAGS(0) <= '1'; -- Carry
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205 Q_FLAGS(1) <= ze(not L_D8); -- Zero
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206 Q_FLAGS(2) <= not L_D8(7); -- Negative
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207 Q_FLAGS(3) <= '0'; -- Overflow
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208 Q_FLAGS(4) <= not L_D8(7); -- Signed
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209
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210 when ALU_DEC =>
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211 L_DOUT <= L_DEC_D & L_DEC_D;
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212 Q_FLAGS(1) <= ze(L_DEC_D); -- Zero
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213 Q_FLAGS(2) <= L_DEC_D(7); -- Negative
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214 if (L_D8 = X"80") then
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215 Q_FLAGS(3) <= '1'; -- Overflow
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216 Q_FLAGS(4) <= not L_DEC_D(7); -- Signed
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| 233 |
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217 else
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218 Q_FLAGS(3) <= '0'; -- Overflow
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219 Q_FLAGS(4) <= L_DEC_D(7); -- Signed
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220 end if;
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221
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222 when ALU_EOR =>
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223 L_DOUT <= L_XOR_DR & L_XOR_DR;
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224 Q_FLAGS(1) <= ze(L_XOR_DR); -- Zero
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225 Q_FLAGS(2) <= L_XOR_DR(7); -- Negative
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226 Q_FLAGS(3) <= '0'; -- Overflow
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227 Q_FLAGS(4) <= L_XOR_DR(7); -- Signed
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228
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229 when ALU_INC =>
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230 L_DOUT <= L_INC_D & L_INC_D;
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231 Q_FLAGS(1) <= ze(L_INC_D); -- Zero
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232 Q_FLAGS(2) <= L_INC_D(7); -- Negative
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233 if (L_D8 = X"7F") then
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234 Q_FLAGS(3) <= '1'; -- Overflow
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235 Q_FLAGS(4) <= not L_INC_D(7); -- Signed
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236 else
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237 Q_FLAGS(3) <= '0'; -- Overflow
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238 Q_FLAGS(4) <= L_INC_D(7); -- Signed
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239 end if;
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240
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241 when ALU_INTR =>
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242 L_DOUT <= I_PC;
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243 Q_FLAGS(7) <= I_IMM(6); -- ena/disable interrupts
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244
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245 when ALU_LSR =>
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246 L_DOUT <= L_LSR_D & L_LSR_D;
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247 Q_FLAGS(0) <= L_D8(0); -- Carry
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248 Q_FLAGS(1) <= ze(L_LSR_D); -- Zero
|
| 265 |
|
|
249 Q_FLAGS(2) <= '0'; -- Negative
|
| 266 |
|
|
250 Q_FLAGS(3) <= L_D8(0); -- Overflow
|
| 267 |
|
|
251 Q_FLAGS(4) <= L_D8(0); -- Signed
|
| 268 |
|
|
252
|
| 269 |
|
|
253 when ALU_D_MV_Q =>
|
| 270 |
|
|
254 L_DOUT <= L_D8 & L_D8;
|
| 271 |
|
|
255
|
| 272 |
|
|
256 when ALU_R_MV_Q =>
|
| 273 |
|
|
257 L_DOUT <= L_RI8 & L_RI8;
|
| 274 |
|
|
258
|
| 275 |
|
|
259 when ALU_MV_16 =>
|
| 276 |
|
|
260 L_DOUT <= I_R(15 downto 8) & L_RI8;
|
| 277 |
|
|
261
|
| 278 |
|
|
262 when ALU_MULT =>
|
| 279 |
|
|
263 Q_FLAGS(0) <= L_PROD(15); -- Carry
|
| 280 |
|
|
264 if I_IMM(7) = '0' then -- MUL
|
| 281 |
|
|
265 L_DOUT <= L_PROD(15 downto 0);
|
| 282 |
|
|
266 Q_FLAGS(1) <= ze(L_PROD(15 downto 8)) -- Zero
|
| 283 |
|
|
267 and ze(L_PROD( 7 downto 0));
|
| 284 |
|
|
268 else -- FMUL
|
| 285 |
|
|
269 L_DOUT <= L_PROD(14 downto 0) & "0";
|
| 286 |
|
|
270 Q_FLAGS(1) <= ze(L_PROD(14 downto 7)) -- Zero
|
| 287 |
|
|
271 and ze(L_PROD( 6 downto 0) & "0");
|
| 288 |
|
|
272 end if;
|
| 289 |
|
|
273
|
| 290 |
|
|
274 when ALU_NEG =>
|
| 291 |
|
|
275 L_DOUT <= L_NEG_D & L_NEG_D;
|
| 292 |
|
|
276 Q_FLAGS(0) <= not ze(L_D8); -- Carry
|
| 293 |
|
|
277 Q_FLAGS(1) <= ze(L_NEG_D); -- Zero
|
| 294 |
|
|
278 Q_FLAGS(2) <= L_NEG_D(7); -- Negative
|
| 295 |
|
|
279 if (L_D8 = X"80") then
|
| 296 |
|
|
280 Q_FLAGS(3) <= '1'; -- Overflow
|
| 297 |
|
|
281 Q_FLAGS(4) <= not L_NEG_D(7); -- Signed
|
| 298 |
|
|
282 else
|
| 299 |
|
|
283 Q_FLAGS(3) <= '0'; -- Overflow
|
| 300 |
|
|
284 Q_FLAGS(4) <= L_NEG_D(7); -- Signed
|
| 301 |
|
|
285 end if;
|
| 302 |
|
|
286 Q_FLAGS(5) <= L_D8(3) or L_NEG_D(3); -- Halfcarry
|
| 303 |
|
|
287
|
| 304 |
|
|
288 when ALU_OR =>
|
| 305 |
|
|
289 L_DOUT <= L_OR_DR & L_OR_DR;
|
| 306 |
|
|
290 Q_FLAGS(1) <= ze(L_OR_DR); -- Zero
|
| 307 |
|
|
291 Q_FLAGS(2) <= L_OR_DR(7); -- Negative
|
| 308 |
|
|
292 Q_FLAGS(3) <= '0'; -- Overflow
|
| 309 |
|
|
293 Q_FLAGS(4) <= L_OR_DR(7); -- Signed
|
| 310 |
|
|
294
|
| 311 |
|
|
295 when ALU_PC_1 => -- ICALL, RCALL
|
| 312 |
|
|
296 L_DOUT <= I_PC + X"0001";
|
| 313 |
|
|
297
|
| 314 |
|
|
298 when ALU_PC_2 => -- CALL
|
| 315 |
|
|
299 L_DOUT <= I_PC + X"0002";
|
| 316 |
|
|
300
|
| 317 |
|
|
301 when ALU_ROR =>
|
| 318 |
|
|
302 L_DOUT <= L_ROR_D & L_ROR_D;
|
| 319 |
|
|
303 Q_FLAGS(1) <= ze(L_ROR_D); -- Zero
|
| 320 |
|
|
304 Q_FLAGS(2) <= I_FLAGS(0); -- Negative
|
| 321 |
|
|
305 Q_FLAGS(3) <= I_FLAGS(0) xor L_D8(0); -- Overflow
|
| 322 |
|
|
306 Q_FLAGS(4) <= I_FLAGS(0); -- Signed
|
| 323 |
|
|
307
|
| 324 |
|
|
308 when ALU_SBC =>
|
| 325 |
|
|
309 L_DOUT <= L_SBC_DR & L_SBC_DR;
|
| 326 |
|
|
310 Q_FLAGS(0) <= cy(L_SBC_DR(7), L_RI8(7), L_D8(7)); -- Carry
|
| 327 |
|
|
311 Q_FLAGS(1) <= ze(L_SBC_DR) and I_FLAGS(1); -- Zero
|
| 328 |
|
|
312 Q_FLAGS(2) <= L_SBC_DR(7); -- Negative
|
| 329 |
|
|
313 Q_FLAGS(3) <= ov(L_SBC_DR(7), L_RI8(7), L_D8(7)); -- Overflow
|
| 330 |
|
|
314 Q_FLAGS(4) <= si(L_SBC_DR(7), L_RI8(7), L_D8(7)); -- Signed
|
| 331 |
|
|
315 Q_FLAGS(5) <= cy(L_SBC_DR(3), L_RI8(3), L_D8(3)); -- Halfcarry
|
| 332 |
|
|
316
|
| 333 |
|
|
317 when ALU_SBIW =>
|
| 334 |
|
|
318 L_DOUT <= L_SBIW_D;
|
| 335 |
|
|
319 Q_FLAGS(0) <= L_SBIW_D(15) and not I_D(15); -- Carry
|
| 336 |
|
|
320 Q_FLAGS(1) <= ze(L_SBIW_D(15 downto 8)) and
|
| 337 |
|
|
321 ze(L_SBIW_D(7 downto 0)); -- Zero
|
| 338 |
|
|
322 Q_FLAGS(2) <= L_SBIW_D(15); -- Negative
|
| 339 |
|
|
323 Q_FLAGS(3) <= I_D(15) and not L_SBIW_D(15); -- Overflow
|
| 340 |
|
|
324 Q_FLAGS(4) <= (L_SBIW_D(15) and not I_D(15))
|
| 341 |
|
|
325 xor (I_D(15) and not L_SBIW_D(15)); -- Signed
|
| 342 |
|
|
326
|
| 343 |
|
|
327 when ALU_SREG =>
|
| 344 |
|
|
328 case I_BIT(2 downto 0) is
|
| 345 |
|
|
329 when "000" => Q_FLAGS(0) <= I_BIT(3);
|
| 346 |
|
|
330 when "001" => Q_FLAGS(1) <= I_BIT(3);
|
| 347 |
|
|
331 when "010" => Q_FLAGS(2) <= I_BIT(3);
|
| 348 |
|
|
332 when "011" => Q_FLAGS(3) <= I_BIT(3);
|
| 349 |
|
|
333 when "100" => Q_FLAGS(4) <= I_BIT(3);
|
| 350 |
|
|
334 when "101" => Q_FLAGS(5) <= I_BIT(3);
|
| 351 |
|
|
335 when "110" => Q_FLAGS(6) <= I_BIT(3);
|
| 352 |
|
|
336 when others => Q_FLAGS(7) <= I_BIT(3);
|
| 353 |
|
|
337 end case;
|
| 354 |
|
|
338
|
| 355 |
|
|
339 when ALU_SUB =>
|
| 356 |
|
|
340 L_DOUT <= L_SUB_DR & L_SUB_DR;
|
| 357 |
|
|
341 Q_FLAGS(0) <= cy(L_SUB_DR(7), L_RI8(7), L_D8(7)); -- Carry
|
| 358 |
|
|
342 Q_FLAGS(1) <= ze(L_SUB_DR); -- Zero
|
| 359 |
|
|
343 Q_FLAGS(2) <= L_SUB_DR(7); -- Negative
|
| 360 |
|
|
344 Q_FLAGS(3) <= ov(L_SUB_DR(7), L_RI8(7), L_D8(7)); -- Overflow
|
| 361 |
|
|
345 Q_FLAGS(4) <= si(L_SUB_DR(7), L_RI8(7), L_D8(7)); -- Signed
|
| 362 |
|
|
346 Q_FLAGS(5) <= cy(L_SUB_DR(3), L_RI8(3), L_D8(3)); -- Halfcarry
|
| 363 |
|
|
347 Q_FLAGS(8) <= ze(L_SUB_DR); -- temp Zero
|
| 364 |
|
|
348
|
| 365 |
|
|
349 when ALU_SWAP =>
|
| 366 |
|
|
350 L_DOUT <= L_SWAP_D & L_SWAP_D;
|
| 367 |
|
|
351
|
| 368 |
|
|
352 when others =>
|
| 369 |
|
|
353 end case;
|
| 370 |
|
|
354 end Process;
|
| 371 |
|
|
355
|
| 372 |
|
|
356 L_D8 <= I_D(15 downto 8) when (I_D0 = '1') else I_D(7 downto 0);
|
| 373 |
|
|
357 L_R8 <= I_R(15 downto 8) when (I_R0 = '1') else I_R(7 downto 0);
|
| 374 |
|
|
358 L_RI8 <= I_IMM when (I_RSEL = RS_IMM) else L_R8;
|
| 375 |
|
|
359
|
| 376 |
|
|
360 L_ADIW_D <= I_D + ("0000000000" & I_IMM(5 downto 0));
|
| 377 |
|
|
361 L_SBIW_D <= I_D - ("0000000000" & I_IMM(5 downto 0));
|
| 378 |
|
|
362 L_ADD_DR <= L_D8 + L_RI8;
|
| 379 |
|
|
363 L_ADC_DR <= L_ADD_DR + ("0000000" & I_FLAGS(0));
|
| 380 |
|
|
364 L_ASR_D <= L_D8(7) & L_D8(7 downto 1);
|
| 381 |
|
|
365 L_AND_DR <= L_D8 and L_RI8;
|
| 382 |
|
|
366 L_DEC_D <= L_D8 - X"01";
|
| 383 |
|
|
367 L_INC_D <= L_D8 + X"01";
|
| 384 |
|
|
368 L_LSR_D <= '0' & L_D8(7 downto 1);
|
| 385 |
|
|
369 L_NEG_D <= X"00" - L_D8;
|
| 386 |
|
|
370 L_NOT_D <= not L_D8;
|
| 387 |
|
|
371 L_OR_DR <= L_D8 or L_RI8;
|
| 388 |
|
|
372 L_PROD <= (L_SIGN_D & L_D8) * (L_SIGN_R & L_R8);
|
| 389 |
|
|
373 L_ROR_D <= I_FLAGS(0) & L_D8(7 downto 1);
|
| 390 |
|
|
374 L_SUB_DR <= L_D8 - L_RI8;
|
| 391 |
|
|
375 L_SBC_DR <= L_SUB_DR - ("0000000" & I_FLAGS(0));
|
| 392 |
|
|
376 L_SIGN_D <= L_D8(7) and I_IMM(6);
|
| 393 |
|
|
377 L_SIGN_R <= L_R8(7) and I_IMM(5);
|
| 394 |
|
|
378 L_SWAP_D <= L_D8(3 downto 0) & L_D8(7 downto 4);
|
| 395 |
|
|
379 L_XOR_DR <= L_D8 xor L_R8;
|
| 396 |
|
|
380
|
| 397 |
|
|
381 Q_DOUT <= (I_DIN & I_DIN) when (I_RSEL = RS_DIN) else L_DOUT;
|
| 398 |
|
|
382
|
| 399 |
|
|
383 end Behavioral;
|
| 400 |
|
|
384
|
| 401 |
|
|
<pre class="filename">
|
| 402 |
|
|
src/alu.vhd
|
| 403 |
|
|
</pre></pre>
|
| 404 |
|
|
<P>
|
| 405 |
|
|
|
| 406 |
|
|
<P><hr><BR>
|
| 407 |
|
|
<table class="ttop"><th class="tpre"><a href="09_Toolchain_Setup.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="11_Listing_of_avr_fpga.vhd.html">Next Lesson</a></th></table>
|
| 408 |
|
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</BODY>
|
| 409 |
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