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<P><table class="ttop"><th class="tpre"><a href="10_Listing_of_alu_vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="12_Listing_of_baudgen.vhd.html">Next Lesson</a></th></table>
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<H1><A NAME="section_1">11 LISTING OF avr_fpga.vhd</A></H1>
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<pre class="vhdl">
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17
  1     -------------------------------------------------------------------------------
18
  2     --
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  3     -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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  4     --
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  5     --  This code is free software: you can redistribute it and/or modify
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  6     --  it under the terms of the GNU General Public License as published by
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  7     --  the Free Software Foundation, either version 3 of the License, or
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  8     --  (at your option) any later version.
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  9     --
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 10     --  This code is distributed in the hope that it will be useful,
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 11     --  but WITHOUT ANY WARRANTY; without even the implied warranty of
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 12     --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 13     --  GNU General Public License for more details.
30
 14     --
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 15     --  You should have received a copy of the GNU General Public License
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 16     --  along with this code (see the file named COPYING).
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 17     --  If not, see http://www.gnu.org/licenses/.
34
 18     --
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 19     -------------------------------------------------------------------------------
36
 20     -------------------------------------------------------------------------------
37
 21     --
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 22     -- Module Name:     avr_fpga - Behavioral
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 23     -- Create Date:     13:51:24 11/07/2009
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 24     -- Description:     top level of a CPU
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 25     --
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 26     -------------------------------------------------------------------------------
43
 27
44
 28     library IEEE;
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 29     use IEEE.STD_LOGIC_1164.ALL;
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 30     use IEEE.STD_LOGIC_ARITH.ALL;
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 31     use IEEE.STD_LOGIC_UNSIGNED.ALL;
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 32
49
 33     entity avr_fpga is
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 34         port (  I_CLK_100   : in  std_logic;
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 35                 I_SWITCH    : in  std_logic_vector(9 downto 0);
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 36                 I_RX        : in  std_logic;
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 37
54
 38                 Q_LEDS      : out std_logic_vector(3 downto 0);
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 39                 Q_7_SEGMENT : out std_logic_vector(6 downto 0);
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 40                 Q_TX        : out std_logic);
57
 41     end avr_fpga;
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 42
59
 43     architecture Behavioral of avr_fpga is
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 44
61
 45     component cpu_core
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 46         port (  I_CLK       : in  std_logic;
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 47                 I_CLR       : in  std_logic;
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 48                 I_INTVEC    : in  std_logic_vector( 5 downto 0);
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 49                 I_DIN       : in  std_logic_vector( 7 downto 0);
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 50
67
 51                 Q_OPC       : out std_logic_vector(15 downto 0);
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 52                 Q_PC        : out std_logic_vector(15 downto 0);
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 53                 Q_DOUT      : out std_logic_vector( 7 downto 0);
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 54                 Q_ADR_IO    : out std_logic_vector( 7 downto 0);
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 55                 Q_RD_IO     : out std_logic;
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 56                 Q_WE_IO     : out std_logic);
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 57     end component;
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 58
75
 59     signal  C_PC            : std_logic_vector(15 downto 0);
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 60     signal  C_OPC           : std_logic_vector(15 downto 0);
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 61     signal  C_ADR_IO        : std_logic_vector( 7 downto 0);
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 62     signal  C_DOUT          : std_logic_vector( 7 downto 0);
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 63     signal  C_RD_IO         : std_logic;
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 64     signal  C_WE_IO         : std_logic;
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 65
82
 66     component io
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 67         port (  I_CLK       : in  std_logic;
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 68                 I_CLR       : in  std_logic;
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 69                 I_ADR_IO    : in  std_logic_vector( 7 downto 0);
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 70                 I_DIN       : in  std_logic_vector( 7 downto 0);
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 71                 I_RD_IO     : in  std_logic;
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 72                 I_WE_IO     : in  std_logic;
89
 73                 I_SWITCH    : in  std_logic_vector( 7 downto 0);
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 74                 I_RX        : in  std_logic;
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 75
92
 76                 Q_7_SEGMENT : out std_logic_vector( 6 downto 0);
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 77                 Q_DOUT      : out std_logic_vector( 7 downto 0);
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 78                 Q_INTVEC    : out std_logic_vector(5 downto 0);
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 79                 Q_LEDS      : out std_logic_vector( 1 downto 0);
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 80                 Q_TX        : out std_logic);
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 81
98
 82     end component;
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 83
100
 84     signal N_INTVEC         : std_logic_vector( 5 downto 0);
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 85     signal N_DOUT           : std_logic_vector( 7 downto 0);
102
 86     signal N_TX             : std_logic;
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 87     signal N_7_SEGMENT      : std_logic_vector( 6 downto 0);
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 88
105
 89     component segment7
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 90         port ( I_CLK        : in  std_logic;
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 91
108
 92                I_CLR        : in  std_logic;
109
 93                I_OPC        : in  std_logic_vector(15 downto 0);
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 94                I_PC         : in  std_logic_vector(15 downto 0);
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 95
112
 96                Q_7_SEGMENT  : out std_logic_vector( 6 downto 0));
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 97     end component;
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 98
115
 99     signal S_7_SEGMENT      : std_logic_vector( 6 downto 0);
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100
117
101     signal L_CLK            : std_logic := '0';
118
102     signal L_CLK_CNT        : std_logic_vector( 2 downto 0) := "000";
119
103     signal L_CLR            : std_logic;            -- reset,  active low
120
104     signal L_CLR_N          : std_logic := '0';     -- reset,  active low
121
105     signal L_C1_N           : std_logic := '0';     -- switch debounce, active low
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106     signal L_C2_N           : std_logic := '0';     -- switch debounce, active low
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107
124
108     begin
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109
126
110         cpu : cpu_core
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111         port map(   I_CLK       => L_CLK,
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112                     I_CLR       => L_CLR,
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113                     I_DIN       => N_DOUT,
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114                     I_INTVEC    => N_INTVEC,
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115
132
116                     Q_ADR_IO    => C_ADR_IO,
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117                     Q_DOUT      => C_DOUT,
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118                     Q_OPC       => C_OPC,
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119                     Q_PC        => C_PC,
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120                     Q_RD_IO     => C_RD_IO,
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121                     Q_WE_IO     => C_WE_IO);
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122
139
123         ino : io
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124         port map(   I_CLK       => L_CLK,
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125                     I_CLR       => L_CLR,
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126                     I_ADR_IO    => C_ADR_IO,
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127                     I_DIN       => C_DOUT,
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128                     I_RD_IO     => C_RD_IO,
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129                     I_RX        => I_RX,
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130                     I_SWITCH    => I_SWITCH(7 downto 0),
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131                     I_WE_IO     => C_WE_IO,
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132
149
133                     Q_7_SEGMENT => N_7_SEGMENT,
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134                     Q_DOUT      => N_DOUT,
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135                     Q_INTVEC    => N_INTVEC,
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136                     Q_LEDS      => Q_LEDS(1 downto 0),
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137                     Q_TX        => N_TX);
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138
155
139         seg : segment7
156
140         port map(   I_CLK       => L_CLK,
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141                     I_CLR       => L_CLR,
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142                     I_OPC       => C_OPC,
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143                     I_PC        => C_PC,
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144
161
145                     Q_7_SEGMENT => S_7_SEGMENT);
162
146
163
147         -- input clock scaler
164
148         --
165
149         clk_div : process(I_CLK_100)
166
150         begin
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151             if (rising_edge(I_CLK_100)) then
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152                 L_CLK_CNT <= L_CLK_CNT + "001";
169
153                 if (L_CLK_CNT = "001") then
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154                     L_CLK_CNT <= "000";
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155                     L_CLK <= not L_CLK;
172
156                 end if;
173
157             end if;
174
158         end process;
175
159
176
160         -- reset button debounce process
177
161         --
178
162         deb : process(L_CLK)
179
163         begin
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164             if (rising_edge(L_CLK)) then
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165                 -- switch debounce
182
166                 if ((I_SWITCH(8) = '0') or (I_SWITCH(9) = '0')) then    -- pushed
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167                     L_CLR_N <= '0';
184
168                     L_C2_N  <= '0';
185
169                     L_C1_N  <= '0';
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170                 else                                                    -- released
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171                     L_CLR_N <= L_C2_N;
188
172                     L_C2_N  <= L_C1_N;
189
173                     L_C1_N  <= '1';
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174                 end if;
191
175             end if;
192
176         end process;
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177
194
178         L_CLR <= not L_CLR_N;
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179
196
180         Q_LEDS(2) <= I_RX;
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181         Q_LEDS(3) <= N_TX;
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182         Q_7_SEGMENT  <= N_7_SEGMENT when (I_SWITCH(7) = '1') else S_7_SEGMENT;
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183         Q_TX <= N_TX;
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184
201
185     end Behavioral;
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186
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<pre class="filename">
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src/avr_fpga.vhd
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</pre></pre>
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<P>
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