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<H1><A NAME="section_1">19 LISTING OF opc_fetch.vhd</A></H1>
 
<pre class="vhdl">
 
  1     -------------------------------------------------------------------------------
  2     --
  3     -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
  4     --
  5     --  This code is free software: you can redistribute it and/or modify
  6     --  it under the terms of the GNU General Public License as published by
  7     --  the Free Software Foundation, either version 3 of the License, or
  8     --  (at your option) any later version.
  9     --
 10     --  This code is distributed in the hope that it will be useful,
 11     --  but WITHOUT ANY WARRANTY; without even the implied warranty of
 12     --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13     --  GNU General Public License for more details.
 14     --
 15     --  You should have received a copy of the GNU General Public License
 16     --  along with this code (see the file named COPYING).
 17     --  If not, see http://www.gnu.org/licenses/.
 18     --
 19     -------------------------------------------------------------------------------
 20     -------------------------------------------------------------------------------
 21     --
 22     -- Module Name:    opc_fetch - Behavioral
 23     -- Create Date:    13:00:44 10/30/2009
 24     -- Description:    the opcode fetch stage of a CPU.
 25     --
 26     -------------------------------------------------------------------------------
 27     --
 28     library IEEE;
 29     use IEEE.std_logic_1164.ALL;
 30     use IEEE.std_logic_ARITH.ALL;
 31     use IEEE.std_logic_UNSIGNED.ALL;
 32
 33     entity opc_fetch is
 34         port (  I_CLK       : in  std_logic;
 35
 36                 I_CLR       : in  std_logic;
 37                 I_INTVEC    : in  std_logic_vector( 5 downto 0);
 38                 I_LOAD_PC   : in  std_logic;
 39                 I_NEW_PC    : in  std_logic_vector(15 downto 0);
 40                 I_PM_ADR    : in  std_logic_vector(11 downto 0);
 41                 I_SKIP      : in  std_logic;
 42
 43                 Q_OPC       : out std_logic_vector(31 downto 0);
 44                 Q_PC        : out std_logic_vector(15 downto 0);
 45                 Q_PM_DOUT   : out std_logic_vector( 7 downto 0);
 46                 Q_T0        : out std_logic);
 47     end opc_fetch;
 48
 49     architecture Behavioral of opc_fetch is
 50
 51     component prog_mem
 52         port (  I_CLK       : in  std_logic;
 53
 54                 I_WAIT      : in  std_logic;
 55                 I_PC        : in  std_logic_vector (15 downto 0);
 56                 I_PM_ADR    : in  std_logic_vector (11 downto 0);
 57
 58                 Q_OPC       : out std_logic_vector (31 downto 0);
 59                 Q_PC        : out std_logic_vector (15 downto 0);
 60                 Q_PM_DOUT   : out std_logic_vector ( 7 downto 0));
 61     end component;
 62
 63     signal P_OPC            : std_logic_vector(31 downto 0);
 64     signal P_PC             : std_logic_vector(15 downto 0);
 65
 66     signal L_INVALIDATE     : std_logic;
 67     signal L_LONG_OP        : std_logic;
 68     signal L_NEXT_PC        : std_logic_vector(15 downto 0);
 69     signal L_PC             : std_logic_vector(15 downto 0);
 70     signal L_T0             : std_logic;
 71     signal L_WAIT           : std_logic;
 72
 73     begin
 74
 75         pmem : prog_mem
 76         port map(   I_CLK       => I_CLK,
 77
 78                     I_WAIT      => L_WAIT,
 79                     I_PC        => L_NEXT_PC,
 80                     I_PM_ADR    => I_PM_ADR,
 81
 82                     Q_OPC       => P_OPC,
 83                     Q_PC        => P_PC,
 84                     Q_PM_DOUT   => Q_PM_DOUT);
 85
 86        lpc: process(I_CLK)
 87         begin
 88             if (rising_edge(I_CLK)) then
 89                 L_PC <= L_NEXT_PC;
 90                 L_T0 <= not L_WAIT;
 91             end if;
 92         end process;
 93
 94         L_INVALIDATE <= I_CLR or I_SKIP;
 95
 96         L_NEXT_PC <= X"0000"        when (I_CLR     = '1')
 97                 else L_PC           when (L_WAIT    = '1')
 98                 else I_NEW_PC       when (I_LOAD_PC = '1')
 99                 else L_PC + X"0002" when (L_LONG_OP = '1')
100                 else L_PC + X"0001";
101
102         -- Two word opcodes:
103         --
104         --        9       3210
105         -- 1001 000d dddd 0000 kkkk kkkk kkkk kkkk - LDS
106         -- 1001 001d dddd 0000 kkkk kkkk kkkk kkkk - SDS
107         -- 1001 010k kkkk 110k kkkk kkkk kkkk kkkk - JMP
108         -- 1001 010k kkkk 111k kkkk kkkk kkkk kkkk - CALL
109         --
110         L_LONG_OP <= '1' when (((P_OPC(15 downto  9) = "1001010") and
111                                 (P_OPC( 3 downto  2) = "11"))       -- JMP, CALL
112                            or  ((P_OPC(15 downto 10) = "100100") and
113                                 (P_OPC( 3 downto  0) = "0000")))    -- LDS, STS
114                 else '0';
115
116         -- Two cycle opcodes:
117         --
118         -- 1001 000d dddd .... - LDS etc.
119         -- 1001 0101 0000 1000 - RET
120         -- 1001 0101 0001 1000 - RETI
121         -- 1001 1001 AAAA Abbb - SBIC
122         -- 1001 1011 AAAA Abbb - SBIS
123         -- 1111 110r rrrr 0bbb - SBRC
124         -- 1111 111r rrrr 0bbb - SBRS
125
126
127         --
128         L_WAIT <= '0'  when (L_INVALIDATE = '1')
129              else '0'  when (I_INTVEC(5)  = '1')
130              else L_T0 when ((P_OPC(15 downto   9) = "1001000" )    -- LDS etc.
131                          or  (P_OPC(15 downto   8) = "10010101")    -- RET etc.
132                          or  ((P_OPC(15 downto 10) = "100110")      -- SBIC, SBIS
133                            and P_OPC(8) = '1')
134                          or  (P_OPC(15 downto  10) = "111111"))     -- SBRC, SBRS
135             else  '0';
136
137         Q_OPC <= X"00000000" when (L_INVALIDATE = '1')
138             else P_OPC       when (I_INTVEC(5) = '0')
139             else (X"000000" & "00" & I_INTVEC);     -- "interrupt opcode"
140
141         Q_PC <= P_PC;
142         Q_T0 <= L_T0;
143
144     end Behavioral;
145
<pre class="filename">
src/opc_fetch.vhd
</pre></pre>
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1	2	jsauermann	`<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"`
2			`"http://www.w3.org/TR/html4/strict.dtd">`
3			`<HTML>`
4			`<HEAD>`
5			`<TITLE>html/Listing_of_opc_fetch.vhd</TITLE>`
6			`<META NAME="generator" CONTENT="HTML::TextToHTML v2.46">`
7			`<LINK REL="stylesheet" TYPE="text/css" HREF="lecture.css">`
8			`</HEAD>`
9			`<BODY>`
10			`<P><table class="ttop"><th class="tpre"><a href="18_Listing_of_opc_deco.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="20_Listing_of_prog_mem_content.vhd.html">Next Lesson</a></th></table>`
11			`<hr>`
12
13			`<H1><A NAME="section_1">19 LISTING OF opc_fetch.vhd</A></H1>`
14
15			`<pre class="vhdl">`
16
17			`1 -------------------------------------------------------------------------------`
18			`2 --`
19			`3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann`
20			`4 --`
21			`5 -- This code is free software: you can redistribute it and/or modify`
22			`6 -- it under the terms of the GNU General Public License as published by`
23			`7 -- the Free Software Foundation, either version 3 of the License, or`
24			`8 -- (at your option) any later version.`
25			`9 --`
26			`10 -- This code is distributed in the hope that it will be useful,`
27			`11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of`
28			`12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
29			`13 -- GNU General Public License for more details.`
30			`14 --`
31			`15 -- You should have received a copy of the GNU General Public License`
32			`16 -- along with this code (see the file named COPYING).`
33			`17 -- If not, see http://www.gnu.org/licenses/.`
34			`18 --`
35			`19 -------------------------------------------------------------------------------`
36			`20 -------------------------------------------------------------------------------`
37			`21 --`
38			`22 -- Module Name: opc_fetch - Behavioral`
39			`23 -- Create Date: 13:00:44 10/30/2009`
40			`24 -- Description: the opcode fetch stage of a CPU.`
41			`25 --`
42			`26 -------------------------------------------------------------------------------`
43			`27 --`
44			`28 library IEEE;`
45			`29 use IEEE.std_logic_1164.ALL;`
46			`30 use IEEE.std_logic_ARITH.ALL;`
47			`31 use IEEE.std_logic_UNSIGNED.ALL;`
48			`32`
49			`33 entity opc_fetch is`
50			`34 port ( I_CLK : in std_logic;`
51			`35`
52			`36 I_CLR : in std_logic;`
53			`37 I_INTVEC : in std_logic_vector( 5 downto 0);`
54			`38 I_LOAD_PC : in std_logic;`
55			`39 I_NEW_PC : in std_logic_vector(15 downto 0);`
56			`40 I_PM_ADR : in std_logic_vector(11 downto 0);`
57			`41 I_SKIP : in std_logic;`
58			`42`
59			`43 Q_OPC : out std_logic_vector(31 downto 0);`
60			`44 Q_PC : out std_logic_vector(15 downto 0);`
61			`45 Q_PM_DOUT : out std_logic_vector( 7 downto 0);`
62			`46 Q_T0 : out std_logic);`
63			`47 end opc_fetch;`
64			`48`
65			`49 architecture Behavioral of opc_fetch is`
66			`50`
67			`51 component prog_mem`
68			`52 port ( I_CLK : in std_logic;`
69			`53`
70			`54 I_WAIT : in std_logic;`
71			`55 I_PC : in std_logic_vector (15 downto 0);`
72			`56 I_PM_ADR : in std_logic_vector (11 downto 0);`
73			`57`
74			`58 Q_OPC : out std_logic_vector (31 downto 0);`
75			`59 Q_PC : out std_logic_vector (15 downto 0);`
76			`60 Q_PM_DOUT : out std_logic_vector ( 7 downto 0));`
77			`61 end component;`
78			`62`
79			`63 signal P_OPC : std_logic_vector(31 downto 0);`
80			`64 signal P_PC : std_logic_vector(15 downto 0);`
81			`65`
82			`66 signal L_INVALIDATE : std_logic;`
83			`67 signal L_LONG_OP : std_logic;`
84			`68 signal L_NEXT_PC : std_logic_vector(15 downto 0);`
85			`69 signal L_PC : std_logic_vector(15 downto 0);`
86			`70 signal L_T0 : std_logic;`
87			`71 signal L_WAIT : std_logic;`
88			`72`
89			`73 begin`
90			`74`
91			`75 pmem : prog_mem`
92			`76 port map( I_CLK => I_CLK,`
93			`77`
94			`78 I_WAIT => L_WAIT,`
95			`79 I_PC => L_NEXT_PC,`
96			`80 I_PM_ADR => I_PM_ADR,`
97			`81`
98			`82 Q_OPC => P_OPC,`
99			`83 Q_PC => P_PC,`
100			`84 Q_PM_DOUT => Q_PM_DOUT);`
101			`85`
102			`86 lpc: process(I_CLK)`
103			`87 begin`
104			`88 if (rising_edge(I_CLK)) then`
105			`89 L_PC <= L_NEXT_PC;`
106			`90 L_T0 <= not L_WAIT;`
107			`91 end if;`
108			`92 end process;`
109			`93`
110			`94 L_INVALIDATE <= I_CLR or I_SKIP;`
111			`95`
112			`96 L_NEXT_PC <= X"0000" when (I_CLR = '1')`
113			`97 else L_PC when (L_WAIT = '1')`
114			`98 else I_NEW_PC when (I_LOAD_PC = '1')`
115			`99 else L_PC + X"0002" when (L_LONG_OP = '1')`
116			`100 else L_PC + X"0001";`
117			`101`
118			`102 -- Two word opcodes:`
119			`103 --`
120			`104 -- 9 3210`
121			`105 -- 1001 000d dddd 0000 kkkk kkkk kkkk kkkk - LDS`
122			`106 -- 1001 001d dddd 0000 kkkk kkkk kkkk kkkk - SDS`
123			`107 -- 1001 010k kkkk 110k kkkk kkkk kkkk kkkk - JMP`
124			`108 -- 1001 010k kkkk 111k kkkk kkkk kkkk kkkk - CALL`
125			`109 --`
126			`110 L_LONG_OP <= '1' when (((P_OPC(15 downto 9) = "1001010") and`
127			`111 (P_OPC( 3 downto 2) = "11")) -- JMP, CALL`
128			`112 or ((P_OPC(15 downto 10) = "100100") and`
129			`113 (P_OPC( 3 downto 0) = "0000"))) -- LDS, STS`
130			`114 else '0';`
131			`115`
132			`116 -- Two cycle opcodes:`
133			`117 --`
134			`118 -- 1001 000d dddd .... - LDS etc.`
135			`119 -- 1001 0101 0000 1000 - RET`
136			`120 -- 1001 0101 0001 1000 - RETI`
137			`121 -- 1001 1001 AAAA Abbb - SBIC`
138			`122 -- 1001 1011 AAAA Abbb - SBIS`
139			`123 -- 1111 110r rrrr 0bbb - SBRC`
140			`124 -- 1111 111r rrrr 0bbb - SBRS`
141			`125`
142			`126`
143			`127 --`
144			`128 L_WAIT <= '0' when (L_INVALIDATE = '1')`
145			`129 else '0' when (I_INTVEC(5) = '1')`
146			`130 else L_T0 when ((P_OPC(15 downto 9) = "1001000" ) -- LDS etc.`
147			`131 or (P_OPC(15 downto 8) = "10010101") -- RET etc.`
148			`132 or ((P_OPC(15 downto 10) = "100110") -- SBIC, SBIS`
149			`133 and P_OPC(8) = '1')`
150			`134 or (P_OPC(15 downto 10) = "111111")) -- SBRC, SBRS`
151			`135 else '0';`
152			`136`
153			`137 Q_OPC <= X"00000000" when (L_INVALIDATE = '1')`
154			`138 else P_OPC when (I_INTVEC(5) = '0')`
155			`139 else (X"000000" & "00" & I_INTVEC); -- "interrupt opcode"`
156			`140`
157			`141 Q_PC <= P_PC;`
158			`142 Q_T0 <= L_T0;`
159			`143`
160			`144 end Behavioral;`
161			`145`
162			`<pre class="filename">`
163			`src/opc_fetch.vhd`
164			`</pre></pre>`
165			`<P>`
166
167			`<P><hr><BR>`
168			`<table class="ttop"><th class="tpre"><a href="18_Listing_of_opc_deco.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="20_Listing_of_prog_mem_content.vhd.html">Next Lesson</a></th></table>`
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