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<P><table class="ttop"><th class="tpre"><a href="18_Listing_of_opc_deco.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="20_Listing_of_prog_mem_content.vhd.html">Next Lesson</a></th></table>
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<H1><A NAME="section_1">19 LISTING OF opc_fetch.vhd</A></H1>
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<pre class="vhdl">
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1 -------------------------------------------------------------------------------
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2 --
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3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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4 --
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5 -- This code is free software: you can redistribute it and/or modify
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6 -- it under the terms of the GNU General Public License as published by
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7 -- the Free Software Foundation, either version 3 of the License, or
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8 -- (at your option) any later version.
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9 --
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10 -- This code is distributed in the hope that it will be useful,
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11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 -- GNU General Public License for more details.
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14 --
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15 -- You should have received a copy of the GNU General Public License
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16 -- along with this code (see the file named COPYING).
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17 -- If not, see http://www.gnu.org/licenses/.
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18 --
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19 -------------------------------------------------------------------------------
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20 -------------------------------------------------------------------------------
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21 --
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22 -- Module Name: opc_fetch - Behavioral
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23 -- Create Date: 13:00:44 10/30/2009
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24 -- Description: the opcode fetch stage of a CPU.
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25 --
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26 -------------------------------------------------------------------------------
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27 --
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28 library IEEE;
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29 use IEEE.std_logic_1164.ALL;
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30 use IEEE.std_logic_ARITH.ALL;
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31 use IEEE.std_logic_UNSIGNED.ALL;
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32
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33 entity opc_fetch is
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34 port ( I_CLK : in std_logic;
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35
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36 I_CLR : in std_logic;
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37 I_INTVEC : in std_logic_vector( 5 downto 0);
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38 I_LOAD_PC : in std_logic;
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39 I_NEW_PC : in std_logic_vector(15 downto 0);
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40 I_PM_ADR : in std_logic_vector(11 downto 0);
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41 I_SKIP : in std_logic;
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42
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43 Q_OPC : out std_logic_vector(31 downto 0);
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44 Q_PC : out std_logic_vector(15 downto 0);
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45 Q_PM_DOUT : out std_logic_vector( 7 downto 0);
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46 Q_T0 : out std_logic);
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47 end opc_fetch;
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48
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49 architecture Behavioral of opc_fetch is
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50
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51 component prog_mem
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52 port ( I_CLK : in std_logic;
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53
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54 I_WAIT : in std_logic;
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55 I_PC : in std_logic_vector (15 downto 0);
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56 I_PM_ADR : in std_logic_vector (11 downto 0);
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57
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58 Q_OPC : out std_logic_vector (31 downto 0);
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59 Q_PC : out std_logic_vector (15 downto 0);
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60 Q_PM_DOUT : out std_logic_vector ( 7 downto 0));
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61 end component;
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62
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63 signal P_OPC : std_logic_vector(31 downto 0);
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64 signal P_PC : std_logic_vector(15 downto 0);
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65
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66 signal L_INVALIDATE : std_logic;
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67 signal L_LONG_OP : std_logic;
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68 signal L_NEXT_PC : std_logic_vector(15 downto 0);
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69 signal L_PC : std_logic_vector(15 downto 0);
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70 signal L_T0 : std_logic;
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71 signal L_WAIT : std_logic;
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72
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73 begin
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74
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75 pmem : prog_mem
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76 port map( I_CLK => I_CLK,
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77
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78 I_WAIT => L_WAIT,
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79 I_PC => L_NEXT_PC,
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80 I_PM_ADR => I_PM_ADR,
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81
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82 Q_OPC => P_OPC,
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83 Q_PC => P_PC,
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84 Q_PM_DOUT => Q_PM_DOUT);
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85
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86 lpc: process(I_CLK)
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87 begin
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88 if (rising_edge(I_CLK)) then
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89 L_PC <= L_NEXT_PC;
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90 L_T0 <= not L_WAIT;
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91 end if;
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92 end process;
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93
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94 L_INVALIDATE <= I_CLR or I_SKIP;
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95
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96 L_NEXT_PC <= X"0000" when (I_CLR = '1')
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97 else L_PC when (L_WAIT = '1')
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98 else I_NEW_PC when (I_LOAD_PC = '1')
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99 else L_PC + X"0002" when (L_LONG_OP = '1')
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100 else L_PC + X"0001";
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101
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102 -- Two word opcodes:
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103 --
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104 -- 9 3210
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105 -- 1001 000d dddd 0000 kkkk kkkk kkkk kkkk - LDS
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106 -- 1001 001d dddd 0000 kkkk kkkk kkkk kkkk - SDS
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107 -- 1001 010k kkkk 110k kkkk kkkk kkkk kkkk - JMP
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108 -- 1001 010k kkkk 111k kkkk kkkk kkkk kkkk - CALL
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109 --
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110 L_LONG_OP <= '1' when (((P_OPC(15 downto 9) = "1001010") and
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111 (P_OPC( 3 downto 2) = "11")) -- JMP, CALL
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112 or ((P_OPC(15 downto 10) = "100100") and
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113 (P_OPC( 3 downto 0) = "0000"))) -- LDS, STS
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114 else '0';
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115
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116 -- Two cycle opcodes:
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117 --
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118 -- 1001 000d dddd .... - LDS etc.
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119 -- 1001 0101 0000 1000 - RET
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120 -- 1001 0101 0001 1000 - RETI
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121 -- 1001 1001 AAAA Abbb - SBIC
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122 -- 1001 1011 AAAA Abbb - SBIS
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123 -- 1111 110r rrrr 0bbb - SBRC
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124 -- 1111 111r rrrr 0bbb - SBRS
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125
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126
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127 --
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128 L_WAIT <= '0' when (L_INVALIDATE = '1')
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129 else '0' when (I_INTVEC(5) = '1')
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130 else L_T0 when ((P_OPC(15 downto 9) = "1001000" ) -- LDS etc.
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131 or (P_OPC(15 downto 8) = "10010101") -- RET etc.
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132 or ((P_OPC(15 downto 10) = "100110") -- SBIC, SBIS
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133 and P_OPC(8) = '1')
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134 or (P_OPC(15 downto 10) = "111111")) -- SBRC, SBRS
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135 else '0';
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136
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137 Q_OPC <= X"00000000" when (L_INVALIDATE = '1')
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138 else P_OPC when (I_INTVEC(5) = '0')
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139 else (X"000000" & "00" & I_INTVEC); -- "interrupt opcode"
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140
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141 Q_PC <= P_PC;
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142 Q_T0 <= L_T0;
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143
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144 end Behavioral;
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145
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<pre class="filename">
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src/opc_fetch.vhd
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</pre></pre>
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<P>
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<P><hr><BR>
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<table class="ttop"><th class="tpre"><a href="18_Listing_of_opc_deco.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="20_Listing_of_prog_mem_content.vhd.html">Next Lesson</a></th></table>
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