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<P><table class="ttop"><th class="tpre"><a href="20_Listing_of_prog_mem_content.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="22_Listing_of_reg_16.vhd.html">Next Lesson</a></th></table>
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<hr>
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<H1><A NAME="section_1">21 LISTING OF prog_mem.vhd</A></H1>
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<pre class="vhdl">
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1 -------------------------------------------------------------------------------
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2 --
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3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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4 --
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5 -- This code is free software: you can redistribute it and/or modify
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6 -- it under the terms of the GNU General Public License as published by
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7 -- the Free Software Foundation, either version 3 of the License, or
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8 -- (at your option) any later version.
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9 --
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10 -- This code is distributed in the hope that it will be useful,
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11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 -- GNU General Public License for more details.
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14 --
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15 -- You should have received a copy of the GNU General Public License
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16 -- along with this code (see the file named COPYING).
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17 -- If not, see http://www.gnu.org/licenses/.
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18 --
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19 -------------------------------------------------------------------------------
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20 -------------------------------------------------------------------------------
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21 --
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22 -- Module Name: prog_mem - Behavioral
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23 -- Create Date: 14:09:04 10/30/2009
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24 -- Description: the program memory of a CPU.
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25 --
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26 ----------------------------------------------------------------------------------
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27 library IEEE;
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28 use IEEE.STD_LOGIC_1164.ALL;
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29 use IEEE.STD_LOGIC_ARITH.ALL;
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30 use IEEE.STD_LOGIC_UNSIGNED.ALL;
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31
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32 -- the content of the program memory.
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33 --
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34 use work.prog_mem_content.all;
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35
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36 entity prog_mem is
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37 port ( I_CLK : in std_logic;
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38
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39 I_WAIT : in std_logic;
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40 I_PC : in std_logic_vector(15 downto 0); -- word address
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41 I_PM_ADR : in std_logic_vector(11 downto 0); -- byte address
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42
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43 Q_OPC : out std_logic_vector(31 downto 0);
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44 Q_PC : out std_logic_vector(15 downto 0);
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45 Q_PM_DOUT : out std_logic_vector( 7 downto 0));
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46 end prog_mem;
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47
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48 architecture Behavioral of prog_mem is
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49
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50 constant zero_256 : bit_vector := X"00000000000000000000000000000000"
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51 & X"00000000000000000000000000000000";
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52
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53 component RAMB4_S4_S4
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54 generic(INIT_00 : bit_vector := zero_256;
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55 INIT_01 : bit_vector := zero_256;
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56 INIT_02 : bit_vector := zero_256;
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57 INIT_03 : bit_vector := zero_256;
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58 INIT_04 : bit_vector := zero_256;
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59 INIT_05 : bit_vector := zero_256;
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60 INIT_06 : bit_vector := zero_256;
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61 INIT_07 : bit_vector := zero_256;
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62 INIT_08 : bit_vector := zero_256;
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63 INIT_09 : bit_vector := zero_256;
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64 INIT_0A : bit_vector := zero_256;
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65 INIT_0B : bit_vector := zero_256;
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66 INIT_0C : bit_vector := zero_256;
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67 INIT_0D : bit_vector := zero_256;
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68 INIT_0E : bit_vector := zero_256;
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69 INIT_0F : bit_vector := zero_256);
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70
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71 port( ADDRA : in std_logic_vector(9 downto 0);
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72 ADDRB : in std_logic_vector(9 downto 0);
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73 CLKA : in std_ulogic;
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74 CLKB : in std_ulogic;
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75 DIA : in std_logic_vector(3 downto 0);
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76 DIB : in std_logic_vector(3 downto 0);
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77 ENA : in std_ulogic;
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78 ENB : in std_ulogic;
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79 RSTA : in std_ulogic;
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80 RSTB : in std_ulogic;
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81 WEA : in std_ulogic;
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82 WEB : in std_ulogic;
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83
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84 DOA : out std_logic_vector(3 downto 0);
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85 DOB : out std_logic_vector(3 downto 0));
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86 end component;
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87
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88 signal M_OPC_E : std_logic_vector(15 downto 0);
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89 signal M_OPC_O : std_logic_vector(15 downto 0);
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90 signal M_PMD_E : std_logic_vector(15 downto 0);
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91 signal M_PMD_O : std_logic_vector(15 downto 0);
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92
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93 signal L_WAIT_N : std_logic;
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94 signal L_PC_0 : std_logic;
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95 signal L_PC_E : std_logic_vector(10 downto 1);
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96 signal L_PC_O : std_logic_vector(10 downto 1);
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97 signal L_PMD : std_logic_vector(15 downto 0);
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98 signal L_PM_ADR_1_0 : std_logic_vector( 1 downto 0);
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99
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100 begin
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101
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102 pe_0 : RAMB4_S4_S4 ---------------------------------------------------------
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103 generic map(INIT_00 => pe_0_00, INIT_01 => pe_0_01, INIT_02 => pe_0_02,
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104 INIT_03 => pe_0_03, INIT_04 => pe_0_04, INIT_05 => pe_0_05,
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105 INIT_06 => pe_0_06, INIT_07 => pe_0_07, INIT_08 => pe_0_08,
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106 INIT_09 => pe_0_09, INIT_0A => pe_0_0A, INIT_0B => pe_0_0B,
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107 INIT_0C => pe_0_0C, INIT_0D => pe_0_0D, INIT_0E => pe_0_0E,
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108 INIT_0F => pe_0_0F)
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109 port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
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110 CLKA => I_CLK, CLKB => I_CLK,
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111 DIA => "0000", DIB => "0000",
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112 ENA => L_WAIT_N, ENB => '1',
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113 RSTA => '0', RSTB => '0',
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114 WEA => '0', WEB => '0',
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115 DOA => M_OPC_E(3 downto 0), DOB => M_PMD_E(3 downto 0));
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116
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117 pe_1 : RAMB4_S4_S4 ---------------------------------------------------------
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118 generic map(INIT_00 => pe_1_00, INIT_01 => pe_1_01, INIT_02 => pe_1_02,
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119 INIT_03 => pe_1_03, INIT_04 => pe_1_04, INIT_05 => pe_1_05,
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120 INIT_06 => pe_1_06, INIT_07 => pe_1_07, INIT_08 => pe_1_08,
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121 INIT_09 => pe_1_09, INIT_0A => pe_1_0A, INIT_0B => pe_1_0B,
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122 INIT_0C => pe_1_0C, INIT_0D => pe_1_0D, INIT_0E => pe_1_0E,
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123 INIT_0F => pe_1_0F)
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124 port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
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125 CLKA => I_CLK, CLKB => I_CLK,
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126 DIA => "0000", DIB => "0000",
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127 ENA => L_WAIT_N, ENB => '1',
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128 RSTA => '0', RSTB => '0',
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129 WEA => '0', WEB => '0',
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130 DOA => M_OPC_E(7 downto 4), DOB => M_PMD_E(7 downto 4));
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131
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132 pe_2 : RAMB4_S4_S4 ---------------------------------------------------------
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133 generic map(INIT_00 => pe_2_00, INIT_01 => pe_2_01, INIT_02 => pe_2_02,
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134 INIT_03 => pe_2_03, INIT_04 => pe_2_04, INIT_05 => pe_2_05,
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135 INIT_06 => pe_2_06, INIT_07 => pe_2_07, INIT_08 => pe_2_08,
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136 INIT_09 => pe_2_09, INIT_0A => pe_2_0A, INIT_0B => pe_2_0B,
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137 INIT_0C => pe_2_0C, INIT_0D => pe_2_0D, INIT_0E => pe_2_0E,
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138 INIT_0F => pe_2_0F)
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139 port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
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140 CLKA => I_CLK, CLKB => I_CLK,
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141 DIA => "0000", DIB => "0000",
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142 ENA => L_WAIT_N, ENB => '1',
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143 RSTA => '0', RSTB => '0',
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144 WEA => '0', WEB => '0',
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145 DOA => M_OPC_E(11 downto 8), DOB => M_PMD_E(11 downto 8));
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146
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147 pe_3 : RAMB4_S4_S4 ---------------------------------------------------------
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148 generic map(INIT_00 => pe_3_00, INIT_01 => pe_3_01, INIT_02 => pe_3_02,
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149 INIT_03 => pe_3_03, INIT_04 => pe_3_04, INIT_05 => pe_3_05,
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150 INIT_06 => pe_3_06, INIT_07 => pe_3_07, INIT_08 => pe_3_08,
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151 INIT_09 => pe_3_09, INIT_0A => pe_3_0A, INIT_0B => pe_3_0B,
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152 INIT_0C => pe_3_0C, INIT_0D => pe_3_0D, INIT_0E => pe_3_0E,
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153 INIT_0F => pe_3_0F)
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154 port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
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155 CLKA => I_CLK, CLKB => I_CLK,
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156 DIA => "0000", DIB => "0000",
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157 ENA => L_WAIT_N, ENB => '1',
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158 RSTA => '0', RSTB => '0',
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159 WEA => '0', WEB => '0',
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160 DOA => M_OPC_E(15 downto 12), DOB => M_PMD_E(15 downto 12));
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161
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162 po_0 : RAMB4_S4_S4 ---------------------------------------------------------
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163 generic map(INIT_00 => po_0_00, INIT_01 => po_0_01, INIT_02 => po_0_02,
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164 INIT_03 => po_0_03, INIT_04 => po_0_04, INIT_05 => po_0_05,
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165 INIT_06 => po_0_06, INIT_07 => po_0_07, INIT_08 => po_0_08,
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166 INIT_09 => po_0_09, INIT_0A => po_0_0A, INIT_0B => po_0_0B,
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167 INIT_0C => po_0_0C, INIT_0D => po_0_0D, INIT_0E => po_0_0E,
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168 INIT_0F => po_0_0F)
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169 port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
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170 CLKA => I_CLK, CLKB => I_CLK,
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171 DIA => "0000", DIB => "0000",
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172 ENA => L_WAIT_N, ENB => '1',
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173 RSTA => '0', RSTB => '0',
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174 WEA => '0', WEB => '0',
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175 DOA => M_OPC_O(3 downto 0), DOB => M_PMD_O(3 downto 0));
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176
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177 po_1 : RAMB4_S4_S4 ---------------------------------------------------------
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178 generic map(INIT_00 => po_1_00, INIT_01 => po_1_01, INIT_02 => po_1_02,
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179 INIT_03 => po_1_03, INIT_04 => po_1_04, INIT_05 => po_1_05,
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180 INIT_06 => po_1_06, INIT_07 => po_1_07, INIT_08 => po_1_08,
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181 INIT_09 => po_1_09, INIT_0A => po_1_0A, INIT_0B => po_1_0B,
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| 198 |
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182 INIT_0C => po_1_0C, INIT_0D => po_1_0D, INIT_0E => po_1_0E,
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| 199 |
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183 INIT_0F => po_1_0F)
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184 port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
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185 CLKA => I_CLK, CLKB => I_CLK,
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186 DIA => "0000", DIB => "0000",
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187 ENA => L_WAIT_N, ENB => '1',
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188 RSTA => '0', RSTB => '0',
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189 WEA => '0', WEB => '0',
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190 DOA => M_OPC_O(7 downto 4), DOB => M_PMD_O(7 downto 4));
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| 207 |
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191
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192 po_2 : RAMB4_S4_S4 ---------------------------------------------------------
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193 generic map(INIT_00 => po_2_00, INIT_01 => po_2_01, INIT_02 => po_2_02,
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| 210 |
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194 INIT_03 => po_2_03, INIT_04 => po_2_04, INIT_05 => po_2_05,
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| 211 |
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195 INIT_06 => po_2_06, INIT_07 => po_2_07, INIT_08 => po_2_08,
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| 212 |
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196 INIT_09 => po_2_09, INIT_0A => po_2_0A, INIT_0B => po_2_0B,
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| 213 |
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197 INIT_0C => po_2_0C, INIT_0D => po_2_0D, INIT_0E => po_2_0E,
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| 214 |
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198 INIT_0F => po_2_0F)
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| 215 |
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199 port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
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| 216 |
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200 CLKA => I_CLK, CLKB => I_CLK,
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| 217 |
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201 DIA => "0000", DIB => "0000",
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| 218 |
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202 ENA => L_WAIT_N, ENB => '1',
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| 219 |
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203 RSTA => '0', RSTB => '0',
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| 220 |
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204 WEA => '0', WEB => '0',
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| 221 |
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205 DOA => M_OPC_O(11 downto 8), DOB => M_PMD_O(11 downto 8));
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| 222 |
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206
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| 223 |
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207 po_3 : RAMB4_S4_S4 ---------------------------------------------------------
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| 224 |
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208 generic map(INIT_00 => po_3_00, INIT_01 => po_3_01, INIT_02 => po_3_02,
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| 225 |
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209 INIT_03 => po_3_03, INIT_04 => po_3_04, INIT_05 => po_3_05,
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| 226 |
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210 INIT_06 => po_3_06, INIT_07 => po_3_07, INIT_08 => po_3_08,
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| 227 |
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211 INIT_09 => po_3_09, INIT_0A => po_3_0A, INIT_0B => po_3_0B,
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| 228 |
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212 INIT_0C => po_3_0C, INIT_0D => po_3_0D, INIT_0E => po_3_0E,
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| 229 |
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213 INIT_0F => po_3_0F)
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| 230 |
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214 port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
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| 231 |
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215 CLKA => I_CLK, CLKB => I_CLK,
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| 232 |
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216 DIA => "0000", DIB => "0000",
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| 233 |
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217 ENA => L_WAIT_N, ENB => '1',
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| 234 |
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218 RSTA => '0', RSTB => '0',
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| 235 |
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219 WEA => '0', WEB => '0',
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| 236 |
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220 DOA => M_OPC_O(15 downto 12), DOB => M_PMD_O(15 downto 12));
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| 237 |
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221
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| 238 |
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222 -- remember I_PC0 and I_PM_ADR for the output mux.
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| 239 |
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223 --
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| 240 |
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224 pc0: process(I_CLK)
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| 241 |
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225 begin
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| 242 |
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226 if (rising_edge(I_CLK)) then
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| 243 |
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227 Q_PC <= I_PC;
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| 244 |
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228 L_PM_ADR_1_0 <= I_PM_ADR(1 downto 0);
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| 245 |
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229 if ((I_WAIT = '0')) then
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| 246 |
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230 L_PC_0 <= I_PC(0);
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| 247 |
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231 end if;
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| 248 |
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232 end if;
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| 249 |
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233 end process;
|
| 250 |
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234
|
| 251 |
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235 L_WAIT_N <= not I_WAIT;
|
| 252 |
|
|
236
|
| 253 |
|
|
237 -- we use two memory blocks _E and _O (even and odd).
|
| 254 |
|
|
238 -- This gives us a quad-port memory so that we can access
|
| 255 |
|
|
239 -- I_PC, I_PC + 1, and PM simultaneously.
|
| 256 |
|
|
240 --
|
| 257 |
|
|
241 -- I_PC and I_PC + 1 are handled by port A of the memory while PM
|
| 258 |
|
|
242 -- is handled by port B.
|
| 259 |
|
|
243 --
|
| 260 |
|
|
244 -- Q_OPC(15 ... 0) shall contain the word addressed by I_PC, while
|
| 261 |
|
|
245 -- Q_OPC(31 ... 16) shall contain the word addressed by I_PC + 1.
|
| 262 |
|
|
246 --
|
| 263 |
|
|
247 -- There are two cases:
|
| 264 |
|
|
248 --
|
| 265 |
|
|
249 -- case A: I_PC is even, thus I_PC + 1 is odd
|
| 266 |
|
|
250 -- case B: I_PC + 1 is odd , thus I_PC is even
|
| 267 |
|
|
251 --
|
| 268 |
|
|
252 L_PC_O <= I_PC(10 downto 1);
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| 269 |
|
|
253 L_PC_E <= I_PC(10 downto 1) + ("000000000" & I_PC(0));
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| 270 |
|
|
254 Q_OPC(15 downto 0) <= M_OPC_E when L_PC_0 = '0' else M_OPC_O;
|
| 271 |
|
|
255 Q_OPC(31 downto 16) <= M_OPC_E when L_PC_0 = '1' else M_OPC_O;
|
| 272 |
|
|
256
|
| 273 |
|
|
257 L_PMD <= M_PMD_E when (L_PM_ADR_1_0(1) = '0') else M_PMD_O;
|
| 274 |
|
|
258 Q_PM_DOUT <= L_PMD(7 downto 0) when (L_PM_ADR_1_0(0) = '0')
|
| 275 |
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|
259 else L_PMD(15 downto 8);
|
| 276 |
|
|
260
|
| 277 |
|
|
261 end Behavioral;
|
| 278 |
|
|
262
|
| 279 |
|
|
<pre class="filename">
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| 280 |
|
|
src/prog_mem.vhd
|
| 281 |
|
|
</pre></pre>
|
| 282 |
|
|
<P>
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| 283 |
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|
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| 284 |
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<P><hr><BR>
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