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<P><table class="ttop"><th class="tpre"><a href="21_Listing_of_prog_mem.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="23_Listing_of_register_file.vhd.html">Next Lesson</a></th></table>
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<H1><A NAME="section_1">22 LISTING OF reg_16.vhd</A></H1>
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<pre class="vhdl">
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1 -------------------------------------------------------------------------------
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2 --
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3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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4 --
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5 -- This code is free software: you can redistribute it and/or modify
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6 -- it under the terms of the GNU General Public License as published by
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7 -- the Free Software Foundation, either version 3 of the License, or
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8 -- (at your option) any later version.
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9 --
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10 -- This code is distributed in the hope that it will be useful,
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11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 -- GNU General Public License for more details.
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14 --
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15 -- You should have received a copy of the GNU General Public License
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16 -- along with this code (see the file named COPYING).
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17 -- If not, see http://www.gnu.org/licenses/.
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18 --
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19 -------------------------------------------------------------------------------
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20 -------------------------------------------------------------------------------
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21 --
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22 -- Module Name: Register - Behavioral
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23 -- Create Date: 12:37:55 10/28/2009
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24 -- Description: a register pair of a CPU.
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25 --
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26 ----------------------------------------------------------------------------------
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27 library IEEE;
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28 use IEEE.STD_LOGIC_1164.ALL;
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29 use IEEE.STD_LOGIC_ARITH.ALL;
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30 use IEEE.STD_LOGIC_UNSIGNED.ALL;
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31
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32 entity reg_16 is
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33 port ( I_CLK : in std_logic;
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34
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35 I_D : in std_logic_vector (15 downto 0);
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36 I_WE : in std_logic_vector ( 1 downto 0);
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37
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38 Q : out std_logic_vector (15 downto 0));
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39 end reg_16;
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40
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41 architecture Behavioral of reg_16 is
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42
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43 signal L : std_logic_vector (15 downto 0) := X"7777";
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44 begin
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45
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46 process(I_CLK)
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47 begin
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48 if (rising_edge(I_CLK)) then
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49 if (I_WE(1) = '1') then
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50 L(15 downto 8) <= I_D(15 downto 8);
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51 end if;
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52 if (I_WE(0) = '1') then
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53 L( 7 downto 0) <= I_D( 7 downto 0);
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54 end if;
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55 end if;
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56 end process;
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57
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58 Q <= L;
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59
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60 end Behavioral;
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61
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<pre class="filename">
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src/reg_16.vhd
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</pre></pre>
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<P>
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<P><hr><BR>
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<table class="ttop"><th class="tpre"><a href="21_Listing_of_prog_mem.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="23_Listing_of_register_file.vhd.html">Next Lesson</a></th></table>
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