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<P><table class="ttop"><th class="tpre"><a href="22_Listing_of_reg_16.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="24_Listing_of_segment7.vhd.html">Next Lesson</a></th></table>
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<hr>
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<H1><A NAME="section_1">23 LISTING OF register_file.vhd</A></H1>
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<pre class="vhdl">
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1 -------------------------------------------------------------------------------
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2 --
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3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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4 --
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5 -- This code is free software: you can redistribute it and/or modify
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6 -- it under the terms of the GNU General Public License as published by
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7 -- the Free Software Foundation, either version 3 of the License, or
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8 -- (at your option) any later version.
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9 --
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10 -- This code is distributed in the hope that it will be useful,
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11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 -- GNU General Public License for more details.
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14 --
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15 -- You should have received a copy of the GNU General Public License
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16 -- along with this code (see the file named COPYING).
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17 -- If not, see http://www.gnu.org/licenses/.
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18 --
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19 -------------------------------------------------------------------------------
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20 -------------------------------------------------------------------------------
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21 --
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22 -- Module Name: RegisterFile - Behavioral
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23 -- Create Date: 12:43:34 10/28/2009
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24 -- Description: a register file (16 register pairs) of a CPU.
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25 --
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26 -------------------------------------------------------------------------------
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27 --
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28 library IEEE;
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29 use IEEE.STD_LOGIC_1164.ALL;
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30 use IEEE.STD_LOGIC_ARITH.ALL;
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31 use IEEE.STD_LOGIC_UNSIGNED.ALL;
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32
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33 use work.common.ALL;
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34
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35 entity register_file is
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36 port ( I_CLK : in std_logic;
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37
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38 I_AMOD : in std_logic_vector( 5 downto 0);
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39 I_COND : in std_logic_vector( 3 downto 0);
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40 I_DDDDD : in std_logic_vector( 4 downto 0);
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41 I_DIN : in std_logic_vector(15 downto 0);
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42 I_FLAGS : in std_logic_vector( 7 downto 0);
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43 I_IMM : in std_logic_vector(15 downto 0);
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44 I_RRRR : in std_logic_vector( 4 downto 1);
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45 I_WE_01 : in std_logic;
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46 I_WE_D : in std_logic_vector( 1 downto 0);
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47 I_WE_F : in std_logic;
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48 I_WE_M : in std_logic;
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49 I_WE_XYZS : in std_logic;
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50
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51 Q_ADR : out std_logic_vector(15 downto 0);
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52 Q_CC : out std_logic;
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53 Q_D : out std_logic_vector(15 downto 0);
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54 Q_FLAGS : out std_logic_vector( 7 downto 0);
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55 Q_R : out std_logic_vector(15 downto 0);
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56 Q_S : out std_logic_vector( 7 downto 0);
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57 Q_Z : out std_logic_vector(15 downto 0));
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58 end register_file;
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59
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60 architecture Behavioral of register_file is
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61
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62 component reg_16
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63 port ( I_CLK : in std_logic;
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64
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65 I_D : in std_logic_vector(15 downto 0);
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66 I_WE : in std_logic_vector( 1 downto 0);
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67
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68 Q : out std_logic_vector(15 downto 0));
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69 end component;
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70
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71 signal R_R00 : std_logic_vector(15 downto 0);
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72 signal R_R02 : std_logic_vector(15 downto 0);
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73 signal R_R04 : std_logic_vector(15 downto 0);
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74 signal R_R06 : std_logic_vector(15 downto 0);
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75 signal R_R08 : std_logic_vector(15 downto 0);
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76 signal R_R10 : std_logic_vector(15 downto 0);
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77 signal R_R12 : std_logic_vector(15 downto 0);
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78 signal R_R14 : std_logic_vector(15 downto 0);
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79 signal R_R16 : std_logic_vector(15 downto 0);
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80 signal R_R18 : std_logic_vector(15 downto 0);
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81 signal R_R20 : std_logic_vector(15 downto 0);
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82 signal R_R22 : std_logic_vector(15 downto 0);
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83 signal R_R24 : std_logic_vector(15 downto 0);
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84 signal R_R26 : std_logic_vector(15 downto 0);
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85 signal R_R28 : std_logic_vector(15 downto 0);
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86 signal R_R30 : std_logic_vector(15 downto 0);
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87 signal R_SP : std_logic_vector(15 downto 0); -- stack pointer
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88
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89 component status_reg is
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90 port ( I_CLK : in std_logic;
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91
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92 I_COND : in std_logic_vector ( 3 downto 0);
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93 I_DIN : in std_logic_vector ( 7 downto 0);
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94 I_FLAGS : in std_logic_vector ( 7 downto 0);
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| 111 |
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95 I_WE_F : in std_logic;
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96 I_WE_SR : in std_logic;
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97
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98 Q : out std_logic_vector ( 7 downto 0);
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99 Q_CC : out std_logic);
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100 end component;
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101
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102 signal S_FLAGS : std_logic_vector( 7 downto 0);
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103
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104 signal L_ADR : std_logic_vector(15 downto 0);
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105 signal L_BASE : std_logic_vector(15 downto 0);
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106 signal L_DDDD : std_logic_vector( 4 downto 1);
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107 signal L_DSP : std_logic_vector(15 downto 0);
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108 signal L_DX : std_logic_vector(15 downto 0);
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109 signal L_DY : std_logic_vector(15 downto 0);
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110 signal L_DZ : std_logic_vector(15 downto 0);
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111 signal L_PRE : std_logic_vector(15 downto 0);
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112 signal L_POST : std_logic_vector(15 downto 0);
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113 signal L_S : std_logic_vector(15 downto 0);
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114 signal L_WE_SP_AMOD : std_logic;
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115 signal L_WE : std_logic_vector(31 downto 0);
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116 signal L_WE_A : std_logic;
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117 signal L_WE_D : std_logic_vector(31 downto 0);
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118 signal L_WE_D2 : std_logic_vector( 1 downto 0);
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119 signal L_WE_DD : std_logic_vector(31 downto 0);
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120 signal L_WE_IO : std_logic_vector(31 downto 0);
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121 signal L_WE_MISC : std_logic_vector(31 downto 0);
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122 signal L_WE_X : std_logic;
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123 signal L_WE_Y : std_logic;
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124 signal L_WE_Z : std_logic;
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125 signal L_WE_SP : std_logic_vector( 1 downto 0);
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126 signal L_WE_SR : std_logic;
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127 signal L_XYZS : std_logic_vector(15 downto 0);
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128
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129 begin
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130
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131 r00: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE( 1 downto 0), I_D => I_DIN, Q => R_R00);
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132 r02: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE( 3 downto 2), I_D => I_DIN, Q => R_R02);
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133 r04: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE( 5 downto 4), I_D => I_DIN, Q => R_R04);
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134 r06: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE( 7 downto 6), I_D => I_DIN, Q => R_R06);
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135 r08: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE( 9 downto 8), I_D => I_DIN, Q => R_R08);
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136 r10: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(11 downto 10), I_D => I_DIN, Q => R_R10);
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137 r12: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(13 downto 12), I_D => I_DIN, Q => R_R12);
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138 r14: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(15 downto 14), I_D => I_DIN, Q => R_R14);
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139 r16: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(17 downto 16), I_D => I_DIN, Q => R_R16);
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| 156 |
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140 r18: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(19 downto 18), I_D => I_DIN, Q => R_R18);
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141 r20: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(21 downto 20), I_D => I_DIN, Q => R_R20);
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142 r22: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(23 downto 22), I_D => I_DIN, Q => R_R22);
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| 159 |
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143 r24: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(25 downto 24), I_D => I_DIN, Q => R_R24);
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144 r26: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(27 downto 26), I_D => L_DX, Q => R_R26);
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145 r28: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(29 downto 28), I_D => L_DY, Q => R_R28);
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146 r30: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(31 downto 30), I_D => L_DZ, Q => R_R30);
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147 sp: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE_SP, I_D => L_DSP, Q => R_SP);
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148
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149 sr: status_reg
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150 port map( I_CLK => I_CLK,
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151 I_COND => I_COND,
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152 I_DIN => I_DIN(7 downto 0),
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153 I_FLAGS => I_FLAGS,
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154 I_WE_F => I_WE_F,
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155 I_WE_SR => L_WE_SR,
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156 Q => S_FLAGS,
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157 Q_CC => Q_CC);
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158
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159 -- The output of the register selected by L_ADR.
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160 --
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161 process(R_R00, R_R02, R_R04, R_R06, R_R08, R_R10, R_R12, R_R14,
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162 R_R16, R_R18, R_R20, R_R22, R_R24, R_R26, R_R28, R_R30,
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163 R_SP, S_FLAGS, L_ADR(6 downto 1))
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164 begin
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165 case L_ADR(6 downto 1) is
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166 when "000000" => L_S <= R_R00;
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167 when "000001" => L_S <= R_R02;
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168 when "000010" => L_S <= R_R04;
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169 when "000011" => L_S <= R_R06;
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170 when "000100" => L_S <= R_R08;
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171 when "000101" => L_S <= R_R10;
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172 when "000110" => L_S <= R_R12;
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173 when "000111" => L_S <= R_R14;
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174 when "001000" => L_S <= R_R16;
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175 when "001001" => L_S <= R_R18;
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176 when "001010" => L_S <= R_R20;
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177 when "001011" => L_S <= R_R22;
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178 when "001100" => L_S <= R_R24;
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179 when "001101" => L_S <= R_R26;
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180 when "001110" => L_S <= R_R28;
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181 when "001111" => L_S <= R_R30;
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| 198 |
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182 when "101111" => L_S <= R_SP ( 7 downto 0) & X"00"; -- SPL
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183 when others => L_S <= S_FLAGS & R_SP (15 downto 8); -- SR/SPH
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184 end case;
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185 end process;
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186
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187 -- The output of the register pair selected by I_DDDDD.
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188 --
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189 process(R_R00, R_R02, R_R04, R_R06, R_R08, R_R10, R_R12, R_R14,
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190 R_R16, R_R18, R_R20, R_R22, R_R24, R_R26, R_R28, R_R30,
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191 I_DDDDD(4 downto 1))
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192 begin
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193 case I_DDDDD(4 downto 1) is
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| 210 |
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194 when "0000" => Q_D <= R_R00;
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| 211 |
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195 when "0001" => Q_D <= R_R02;
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196 when "0010" => Q_D <= R_R04;
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| 213 |
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197 when "0011" => Q_D <= R_R06;
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| 214 |
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198 when "0100" => Q_D <= R_R08;
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| 215 |
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199 when "0101" => Q_D <= R_R10;
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| 216 |
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200 when "0110" => Q_D <= R_R12;
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| 217 |
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201 when "0111" => Q_D <= R_R14;
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| 218 |
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202 when "1000" => Q_D <= R_R16;
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| 219 |
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203 when "1001" => Q_D <= R_R18;
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| 220 |
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204 when "1010" => Q_D <= R_R20;
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| 221 |
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205 when "1011" => Q_D <= R_R22;
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| 222 |
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206 when "1100" => Q_D <= R_R24;
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| 223 |
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207 when "1101" => Q_D <= R_R26;
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| 224 |
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208 when "1110" => Q_D <= R_R28;
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| 225 |
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209 when others => Q_D <= R_R30;
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| 226 |
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210 end case;
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| 227 |
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211 end process;
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| 228 |
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212
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| 229 |
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213 -- The output of the register pair selected by I_RRRR.
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| 230 |
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214 --
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| 231 |
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215 process(R_R00, R_R02, R_R04, R_R06, R_R08, R_R10, R_R12, R_R14,
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| 232 |
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216 R_R16, R_R18, R_R20, R_R22, R_R24, R_R26, R_R28, R_R30, I_RRRR)
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| 233 |
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217 begin
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| 234 |
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218 case I_RRRR is
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| 235 |
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219 when "0000" => Q_R <= R_R00;
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220 when "0001" => Q_R <= R_R02;
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| 237 |
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221 when "0010" => Q_R <= R_R04;
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| 238 |
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222 when "0011" => Q_R <= R_R06;
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| 239 |
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223 when "0100" => Q_R <= R_R08;
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| 240 |
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224 when "0101" => Q_R <= R_R10;
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| 241 |
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225 when "0110" => Q_R <= R_R12;
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| 242 |
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226 when "0111" => Q_R <= R_R14;
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| 243 |
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227 when "1000" => Q_R <= R_R16;
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| 244 |
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228 when "1001" => Q_R <= R_R18;
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| 245 |
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229 when "1010" => Q_R <= R_R20;
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| 246 |
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230 when "1011" => Q_R <= R_R22;
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| 247 |
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231 when "1100" => Q_R <= R_R24;
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| 248 |
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232 when "1101" => Q_R <= R_R26;
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| 249 |
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233 when "1110" => Q_R <= R_R28;
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| 250 |
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234 when others => Q_R <= R_R30;
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| 251 |
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235 end case;
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| 252 |
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236 end process;
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| 253 |
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237
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| 254 |
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238 -- the base value of the X/Y/Z/SP register as per I_AMOD.
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| 255 |
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239 --
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| 256 |
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240 process(I_AMOD(2 downto 0), I_IMM, R_SP, R_R26, R_R28, R_R30)
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| 257 |
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241 begin
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| 258 |
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242 case I_AMOD(2 downto 0) is
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| 259 |
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243 when AS_SP => L_BASE <= R_SP;
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| 260 |
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244 when AS_Z => L_BASE <= R_R30;
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| 261 |
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|
245 when AS_Y => L_BASE <= R_R28;
|
| 262 |
|
|
246 when AS_X => L_BASE <= R_R26;
|
| 263 |
|
|
247 when AS_IMM => L_BASE <= I_IMM;
|
| 264 |
|
|
248 when others => L_BASE <= X"0000";
|
| 265 |
|
|
249 end case;
|
| 266 |
|
|
250 end process;
|
| 267 |
|
|
251
|
| 268 |
|
|
252 -- the value of the X/Y/Z/SP register after a potential PRE-decrement
|
| 269 |
|
|
253 -- (by 1 or 2) and POST-increment (by 1 or 2).
|
| 270 |
|
|
254 --
|
| 271 |
|
|
255 process(I_AMOD(5 downto 3), I_IMM)
|
| 272 |
|
|
256 begin
|
| 273 |
|
|
257 case I_AMOD(5 downto 3) is
|
| 274 |
|
|
258 when AO_0 => L_PRE <= X"0000"; L_POST <= X"0000";
|
| 275 |
|
|
259 when AO_i => L_PRE <= X"0000"; L_POST <= X"0001";
|
| 276 |
|
|
260 when AO_ii => L_PRE <= X"0000"; L_POST <= X"0002";
|
| 277 |
|
|
261 when AO_q => L_PRE <= I_IMM; L_POST <= X"0000";
|
| 278 |
|
|
262 when AO_d => L_PRE <= X"FFFF"; L_POST <= X"FFFF";
|
| 279 |
|
|
263 when AO_dd => L_PRE <= X"FFFE"; L_POST <= X"FFFE";
|
| 280 |
|
|
264 when others => L_PRE <= X"0000"; L_POST <= X"0000";
|
| 281 |
|
|
265 end case;
|
| 282 |
|
|
266 end process;
|
| 283 |
|
|
267
|
| 284 |
|
|
268 L_XYZS <= L_BASE + L_POST;
|
| 285 |
|
|
269 L_ADR <= L_BASE + L_PRE;
|
| 286 |
|
|
270
|
| 287 |
|
|
271 L_WE_A <= I_WE_M when (L_ADR(15 downto 5) = "00000000000") else '0';
|
| 288 |
|
|
272 L_WE_SR <= I_WE_M when (L_ADR = X"005F") else '0';
|
| 289 |
|
|
273 L_WE_SP_AMOD <= I_WE_XYZS when (I_AMOD(2 downto 0) = AS_SP) else '0';
|
| 290 |
|
|
274 L_WE_SP(1) <= I_WE_M when (L_ADR = X"005E") else L_WE_SP_AMOD;
|
| 291 |
|
|
275 L_WE_SP(0) <= I_WE_M when (L_ADR = X"005D") else L_WE_SP_AMOD;
|
| 292 |
|
|
276
|
| 293 |
|
|
277 L_DX <= L_XYZS when (L_WE_MISC(26) = '1') else I_DIN;
|
| 294 |
|
|
278 L_DY <= L_XYZS when (L_WE_MISC(28) = '1') else I_DIN;
|
| 295 |
|
|
279 L_DZ <= L_XYZS when (L_WE_MISC(30) = '1') else I_DIN;
|
| 296 |
|
|
280 L_DSP <= L_XYZS when (I_AMOD(3 downto 0) = AM_WS) else I_DIN;
|
| 297 |
|
|
281
|
| 298 |
|
|
282 -- the WE signals for the differen registers.
|
| 299 |
|
|
283 --
|
| 300 |
|
|
284 -- case 1: write to an 8-bit register addressed by DDDDD.
|
| 301 |
|
|
285 --
|
| 302 |
|
|
286 -- I_WE_D(0) = '1' and I_DDDDD matches,
|
| 303 |
|
|
287 --
|
| 304 |
|
|
288 L_WE_D( 0) <= I_WE_D(0) when (I_DDDDD = "00000") else '0';
|
| 305 |
|
|
289 L_WE_D( 1) <= I_WE_D(0) when (I_DDDDD = "00001") else '0';
|
| 306 |
|
|
290 L_WE_D( 2) <= I_WE_D(0) when (I_DDDDD = "00010") else '0';
|
| 307 |
|
|
291 L_WE_D( 3) <= I_WE_D(0) when (I_DDDDD = "00011") else '0';
|
| 308 |
|
|
292 L_WE_D( 4) <= I_WE_D(0) when (I_DDDDD = "00100") else '0';
|
| 309 |
|
|
293 L_WE_D( 5) <= I_WE_D(0) when (I_DDDDD = "00101") else '0';
|
| 310 |
|
|
294 L_WE_D( 6) <= I_WE_D(0) when (I_DDDDD = "00110") else '0';
|
| 311 |
|
|
295 L_WE_D( 7) <= I_WE_D(0) when (I_DDDDD = "00111") else '0';
|
| 312 |
|
|
296 L_WE_D( 8) <= I_WE_D(0) when (I_DDDDD = "01000") else '0';
|
| 313 |
|
|
297 L_WE_D( 9) <= I_WE_D(0) when (I_DDDDD = "01001") else '0';
|
| 314 |
|
|
298 L_WE_D(10) <= I_WE_D(0) when (I_DDDDD = "01010") else '0';
|
| 315 |
|
|
299 L_WE_D(11) <= I_WE_D(0) when (I_DDDDD = "01011") else '0';
|
| 316 |
|
|
300 L_WE_D(12) <= I_WE_D(0) when (I_DDDDD = "01100") else '0';
|
| 317 |
|
|
301 L_WE_D(13) <= I_WE_D(0) when (I_DDDDD = "01101") else '0';
|
| 318 |
|
|
302 L_WE_D(14) <= I_WE_D(0) when (I_DDDDD = "01110") else '0';
|
| 319 |
|
|
303 L_WE_D(15) <= I_WE_D(0) when (I_DDDDD = "01111") else '0';
|
| 320 |
|
|
304 L_WE_D(16) <= I_WE_D(0) when (I_DDDDD = "10000") else '0';
|
| 321 |
|
|
305 L_WE_D(17) <= I_WE_D(0) when (I_DDDDD = "10001") else '0';
|
| 322 |
|
|
306 L_WE_D(18) <= I_WE_D(0) when (I_DDDDD = "10010") else '0';
|
| 323 |
|
|
307 L_WE_D(19) <= I_WE_D(0) when (I_DDDDD = "10011") else '0';
|
| 324 |
|
|
308 L_WE_D(20) <= I_WE_D(0) when (I_DDDDD = "10100") else '0';
|
| 325 |
|
|
309 L_WE_D(21) <= I_WE_D(0) when (I_DDDDD = "10101") else '0';
|
| 326 |
|
|
310 L_WE_D(22) <= I_WE_D(0) when (I_DDDDD = "10110") else '0';
|
| 327 |
|
|
311 L_WE_D(23) <= I_WE_D(0) when (I_DDDDD = "10111") else '0';
|
| 328 |
|
|
312 L_WE_D(24) <= I_WE_D(0) when (I_DDDDD = "11000") else '0';
|
| 329 |
|
|
313 L_WE_D(25) <= I_WE_D(0) when (I_DDDDD = "11001") else '0';
|
| 330 |
|
|
314 L_WE_D(26) <= I_WE_D(0) when (I_DDDDD = "11010") else '0';
|
| 331 |
|
|
315 L_WE_D(27) <= I_WE_D(0) when (I_DDDDD = "11011") else '0';
|
| 332 |
|
|
316 L_WE_D(28) <= I_WE_D(0) when (I_DDDDD = "11100") else '0';
|
| 333 |
|
|
317 L_WE_D(29) <= I_WE_D(0) when (I_DDDDD = "11101") else '0';
|
| 334 |
|
|
318 L_WE_D(30) <= I_WE_D(0) when (I_DDDDD = "11110") else '0';
|
| 335 |
|
|
319 L_WE_D(31) <= I_WE_D(0) when (I_DDDDD = "11111") else '0';
|
| 336 |
|
|
320
|
| 337 |
|
|
321 --
|
| 338 |
|
|
322 -- case 2: write to a 16-bit register pair addressed by DDDD.
|
| 339 |
|
|
323 --
|
| 340 |
|
|
324 -- I_WE_DD(1) = '1' and L_DDDD matches,
|
| 341 |
|
|
325 --
|
| 342 |
|
|
326 L_DDDD <= I_DDDDD(4 downto 1);
|
| 343 |
|
|
327 L_WE_D2 <= I_WE_D(1) & I_WE_D(1);
|
| 344 |
|
|
328 L_WE_DD( 1 downto 0) <= L_WE_D2 when (L_DDDD = "0000") else "00";
|
| 345 |
|
|
329 L_WE_DD( 3 downto 2) <= L_WE_D2 when (L_DDDD = "0001") else "00";
|
| 346 |
|
|
330 L_WE_DD( 5 downto 4) <= L_WE_D2 when (L_DDDD = "0010") else "00";
|
| 347 |
|
|
331 L_WE_DD( 7 downto 6) <= L_WE_D2 when (L_DDDD = "0011") else "00";
|
| 348 |
|
|
332 L_WE_DD( 9 downto 8) <= L_WE_D2 when (L_DDDD = "0100") else "00";
|
| 349 |
|
|
333 L_WE_DD(11 downto 10) <= L_WE_D2 when (L_DDDD = "0101") else "00";
|
| 350 |
|
|
334 L_WE_DD(13 downto 12) <= L_WE_D2 when (L_DDDD = "0110") else "00";
|
| 351 |
|
|
335 L_WE_DD(15 downto 14) <= L_WE_D2 when (L_DDDD = "0111") else "00";
|
| 352 |
|
|
336 L_WE_DD(17 downto 16) <= L_WE_D2 when (L_DDDD = "1000") else "00";
|
| 353 |
|
|
337 L_WE_DD(19 downto 18) <= L_WE_D2 when (L_DDDD = "1001") else "00";
|
| 354 |
|
|
338 L_WE_DD(21 downto 20) <= L_WE_D2 when (L_DDDD = "1010") else "00";
|
| 355 |
|
|
339 L_WE_DD(23 downto 22) <= L_WE_D2 when (L_DDDD = "1011") else "00";
|
| 356 |
|
|
340 L_WE_DD(25 downto 24) <= L_WE_D2 when (L_DDDD = "1100") else "00";
|
| 357 |
|
|
341 L_WE_DD(27 downto 26) <= L_WE_D2 when (L_DDDD = "1101") else "00";
|
| 358 |
|
|
342 L_WE_DD(29 downto 28) <= L_WE_D2 when (L_DDDD = "1110") else "00";
|
| 359 |
|
|
343 L_WE_DD(31 downto 30) <= L_WE_D2 when (L_DDDD = "1111") else "00";
|
| 360 |
|
|
344
|
| 361 |
|
|
345 --
|
| 362 |
|
|
346 -- case 3: write to an 8-bit register pair addressed by an I/O address.
|
| 363 |
|
|
347 --
|
| 364 |
|
|
348 -- L_WE_A = '1' and L_ADR(4 downto 0) matches
|
| 365 |
|
|
349 --
|
| 366 |
|
|
350 L_WE_IO( 0) <= L_WE_A when (L_ADR(4 downto 0) = "00000") else '0';
|
| 367 |
|
|
351 L_WE_IO( 1) <= L_WE_A when (L_ADR(4 downto 0) = "00001") else '0';
|
| 368 |
|
|
352 L_WE_IO( 2) <= L_WE_A when (L_ADR(4 downto 0) = "00010") else '0';
|
| 369 |
|
|
353 L_WE_IO( 3) <= L_WE_A when (L_ADR(4 downto 0) = "00011") else '0';
|
| 370 |
|
|
354 L_WE_IO( 4) <= L_WE_A when (L_ADR(4 downto 0) = "00100") else '0';
|
| 371 |
|
|
355 L_WE_IO( 5) <= L_WE_A when (L_ADR(4 downto 0) = "00101") else '0';
|
| 372 |
|
|
356 L_WE_IO( 6) <= L_WE_A when (L_ADR(4 downto 0) = "00110") else '0';
|
| 373 |
|
|
357 L_WE_IO( 7) <= L_WE_A when (L_ADR(4 downto 0) = "00111") else '0';
|
| 374 |
|
|
358 L_WE_IO( 8) <= L_WE_A when (L_ADR(4 downto 0) = "01000") else '0';
|
| 375 |
|
|
359 L_WE_IO( 9) <= L_WE_A when (L_ADR(4 downto 0) = "01001") else '0';
|
| 376 |
|
|
360 L_WE_IO(10) <= L_WE_A when (L_ADR(4 downto 0) = "01010") else '0';
|
| 377 |
|
|
361 L_WE_IO(11) <= L_WE_A when (L_ADR(4 downto 0) = "01011") else '0';
|
| 378 |
|
|
362 L_WE_IO(12) <= L_WE_A when (L_ADR(4 downto 0) = "01100") else '0';
|
| 379 |
|
|
363 L_WE_IO(13) <= L_WE_A when (L_ADR(4 downto 0) = "01101") else '0';
|
| 380 |
|
|
364 L_WE_IO(14) <= L_WE_A when (L_ADR(4 downto 0) = "01110") else '0';
|
| 381 |
|
|
365 L_WE_IO(15) <= L_WE_A when (L_ADR(4 downto 0) = "01111") else '0';
|
| 382 |
|
|
366 L_WE_IO(16) <= L_WE_A when (L_ADR(4 downto 0) = "10000") else '0';
|
| 383 |
|
|
367 L_WE_IO(17) <= L_WE_A when (L_ADR(4 downto 0) = "10001") else '0';
|
| 384 |
|
|
368 L_WE_IO(18) <= L_WE_A when (L_ADR(4 downto 0) = "10010") else '0';
|
| 385 |
|
|
369 L_WE_IO(19) <= L_WE_A when (L_ADR(4 downto 0) = "10011") else '0';
|
| 386 |
|
|
370 L_WE_IO(20) <= L_WE_A when (L_ADR(4 downto 0) = "10100") else '0';
|
| 387 |
|
|
371 L_WE_IO(21) <= L_WE_A when (L_ADR(4 downto 0) = "10101") else '0';
|
| 388 |
|
|
372 L_WE_IO(22) <= L_WE_A when (L_ADR(4 downto 0) = "10110") else '0';
|
| 389 |
|
|
373 L_WE_IO(23) <= L_WE_A when (L_ADR(4 downto 0) = "10111") else '0';
|
| 390 |
|
|
374 L_WE_IO(24) <= L_WE_A when (L_ADR(4 downto 0) = "11000") else '0';
|
| 391 |
|
|
375 L_WE_IO(25) <= L_WE_A when (L_ADR(4 downto 0) = "11001") else '0';
|
| 392 |
|
|
376 L_WE_IO(26) <= L_WE_A when (L_ADR(4 downto 0) = "11010") else '0';
|
| 393 |
|
|
377 L_WE_IO(27) <= L_WE_A when (L_ADR(4 downto 0) = "11011") else '0';
|
| 394 |
|
|
378 L_WE_IO(28) <= L_WE_A when (L_ADR(4 downto 0) = "11100") else '0';
|
| 395 |
|
|
379 L_WE_IO(29) <= L_WE_A when (L_ADR(4 downto 0) = "11101") else '0';
|
| 396 |
|
|
380 L_WE_IO(30) <= L_WE_A when (L_ADR(4 downto 0) = "11110") else '0';
|
| 397 |
|
|
381 L_WE_IO(31) <= L_WE_A when (L_ADR(4 downto 0) = "11111") else '0';
|
| 398 |
|
|
382
|
| 399 |
|
|
383 -- case 4 special cases.
|
| 400 |
|
|
384 -- 4a. WE_01 for register pair 0/1 (multiplication opcode).
|
| 401 |
|
|
385 -- 4b. I_WE_XYZS for X (register pairs 26/27) and I_AMOD matches
|
| 402 |
|
|
386 -- 4c. I_WE_XYZS for Y (register pairs 28/29) and I_AMOD matches
|
| 403 |
|
|
387 -- 4d. I_WE_XYZS for Z (register pairs 30/31) and I_AMOD matches
|
| 404 |
|
|
388 --
|
| 405 |
|
|
389 L_WE_X <= I_WE_XYZS when (I_AMOD(3 downto 0) = AM_WX) else '0';
|
| 406 |
|
|
390 L_WE_Y <= I_WE_XYZS when (I_AMOD(3 downto 0) = AM_WY) else '0';
|
| 407 |
|
|
391 L_WE_Z <= I_WE_XYZS when (I_AMOD(3 downto 0) = AM_WZ) else '0';
|
| 408 |
|
|
392 L_WE_MISC <= L_WE_Z & L_WE_Z & -- -Z and Z+ address modes r30
|
| 409 |
|
|
393 L_WE_Y & L_WE_Y & -- -Y and Y+ address modes r28
|
| 410 |
|
|
394 L_WE_X & L_WE_X & -- -X and X+ address modes r26
|
| 411 |
|
|
395 X"000000" & -- never r24 - r02
|
| 412 |
|
|
396 I_WE_01 & I_WE_01; -- multiplication result r00
|
| 413 |
|
|
397
|
| 414 |
|
|
398 L_WE <= L_WE_D or L_WE_DD or L_WE_IO or L_WE_MISC;
|
| 415 |
|
|
399
|
| 416 |
|
|
400 Q_S <= L_S( 7 downto 0) when (L_ADR(0) = '0') else L_S(15 downto 8);
|
| 417 |
|
|
401 Q_FLAGS <= S_FLAGS;
|
| 418 |
|
|
402 Q_Z <= R_R30;
|
| 419 |
|
|
403 Q_ADR <= L_ADR;
|
| 420 |
|
|
404
|
| 421 |
|
|
405 end Behavioral;
|
| 422 |
|
|
406
|
| 423 |
|
|
<pre class="filename">
|
| 424 |
|
|
src/register_file.vhd
|
| 425 |
|
|
</pre></pre>
|
| 426 |
|
|
<P>
|
| 427 |
|
|
|
| 428 |
|
|
<P><hr><BR>
|
| 429 |
|
|
<table class="ttop"><th class="tpre"><a href="22_Listing_of_reg_16.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="24_Listing_of_segment7.vhd.html">Next Lesson</a></th></table>
|
| 430 |
|
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|
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