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<P><table class="ttop"><th class="tpre"><a href="24_Listing_of_segment7.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="26_Listing_of_uart_rx.vhd.html">Next Lesson</a></th></table>
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<hr>
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<H1><A NAME="section_1">25 LISTING OF status_reg.vhd</A></H1>
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<pre class="vhdl">
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1 -------------------------------------------------------------------------------
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2 --
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3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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4 --
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5 -- This code is free software: you can redistribute it and/or modify
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6 -- it under the terms of the GNU General Public License as published by
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7 -- the Free Software Foundation, either version 3 of the License, or
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8 -- (at your option) any later version.
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9 --
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10 -- This code is distributed in the hope that it will be useful,
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11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 -- GNU General Public License for more details.
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14 --
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15 -- You should have received a copy of the GNU General Public License
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16 -- along with this code (see the file named COPYING).
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17 -- If not, see http://www.gnu.org/licenses/.
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18 --
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19 -------------------------------------------------------------------------------
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20 -------------------------------------------------------------------------------
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21 --
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22 -- Module Name: Register - Behavioral
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23 -- Create Date: 16:15:54 12/26/2009
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24 -- Description: the status register of a CPU.
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25 --
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26 ----------------------------------------------------------------------------------
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27 library IEEE;
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28 use IEEE.STD_LOGIC_1164.ALL;
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29 use IEEE.STD_LOGIC_ARITH.ALL;
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30 use IEEE.STD_LOGIC_UNSIGNED.ALL;
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31
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32 entity status_reg is
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33 port ( I_CLK : in std_logic;
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34
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35 I_COND : in std_logic_vector ( 3 downto 0);
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36 I_DIN : in std_logic_vector ( 7 downto 0);
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37 I_FLAGS : in std_logic_vector ( 7 downto 0);
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38 I_WE_F : in std_logic;
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39 I_WE_SR : in std_logic;
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40
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41 Q : out std_logic_vector ( 7 downto 0);
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42 Q_CC : out std_logic);
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43 end status_reg;
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44
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45 architecture Behavioral of status_reg is
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46
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47 signal L : std_logic_vector ( 7 downto 0);
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48 begin
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49
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50 process(I_CLK)
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51 begin
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52 if (rising_edge(I_CLK)) then
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53 if (I_WE_F = '1') then -- write flags (from ALU)
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54 L <= I_FLAGS;
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55 elsif (I_WE_SR = '1') then -- write I/O
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56 L <= I_DIN;
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57 end if;
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58 end if;
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59 end process;
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60
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61 cond: process(I_COND, L)
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62 begin
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63 case I_COND(2 downto 0) is
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64 when "000" => Q_CC <= L(0) xor I_COND(3);
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65 when "001" => Q_CC <= L(1) xor I_COND(3);
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66 when "010" => Q_CC <= L(2) xor I_COND(3);
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67 when "011" => Q_CC <= L(3) xor I_COND(3);
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68 when "100" => Q_CC <= L(4) xor I_COND(3);
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69 when "101" => Q_CC <= L(5) xor I_COND(3);
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70 when "110" => Q_CC <= L(6) xor I_COND(3);
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71 when others => Q_CC <= L(7) xor I_COND(3);
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72 end case;
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73 end process;
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74
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75 Q <= L;
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76
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77 end Behavioral;
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78
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<pre class="filename">
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src/status_reg.vhd
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</pre></pre>
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<P>
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<P><hr><BR>
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<table class="ttop"><th class="tpre"><a href="24_Listing_of_segment7.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="26_Listing_of_uart_rx.vhd.html">Next Lesson</a></th></table>
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