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<P><table class="ttop"><th class="tpre"><a href="27_Listing_of_uart_tx.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="29_Listing_of_test_tb.vhd.html">Next Lesson</a></th></table>
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<H1><A NAME="section_1">28 LISTING OF RAMB4_S4_S4.vhd</A></H1>
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<pre class="vhdl">
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17 
  1     -------------------------------------------------------------------------------
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  2     --
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  3     -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
20 
  4     --
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  5     --  This code is free software: you can redistribute it and/or modify
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  6     --  it under the terms of the GNU General Public License as published by
23 
  7     --  the Free Software Foundation, either version 3 of the License, or
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  8     --  (at your option) any later version.
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  9     --
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 10     --  This code is distributed in the hope that it will be useful,
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 11     --  but WITHOUT ANY WARRANTY; without even the implied warranty of
28 
 12     --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 13     --  GNU General Public License for more details.
30 
 14     --
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 15     --  You should have received a copy of the GNU General Public License
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 16     --  along with this code (see the file named COPYING).
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 17     --  If not, see http://www.gnu.org/licenses/.
34 
 18     --
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 19     -------------------------------------------------------------------------------
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 20     -------------------------------------------------------------------------------
37 
 21     --
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 22     -- Module Name:    prog_mem - Behavioral
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 23     -- Create Date:    14:09:04 10/30/2009
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 24     -- Description:    a block memory module
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 25     --
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 26     -------------------------------------------------------------------------------
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 27
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 28     library IEEE;
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 29     use IEEE.STD_LOGIC_1164.ALL;
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 30     use IEEE.STD_LOGIC_ARITH.ALL;
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 31     use IEEE.STD_LOGIC_UNSIGNED.ALL;
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 32
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 33     entity RAMB4_S4_S4 is
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 34         generic(INIT_00 : bit_vector := X"00000000000000000000000000000000"
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 35                                       &  "00000000000000000000000000000000";
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 36                 INIT_01 : bit_vector := X"00000000000000000000000000000000"
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 37                                       & X"00000000000000000000000000000000";
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 38                 INIT_02 : bit_vector := X"00000000000000000000000000000000"
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 39                                       & X"00000000000000000000000000000000";
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 40                 INIT_03 : bit_vector := X"00000000000000000000000000000000"
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 41                                       & X"00000000000000000000000000000000";
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 42                 INIT_04 : bit_vector := X"00000000000000000000000000000000"
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 43                                       & X"00000000000000000000000000000000";
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 44                 INIT_05 : bit_vector := X"00000000000000000000000000000000"
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 45                                       & X"00000000000000000000000000000000";
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 46                 INIT_06 : bit_vector := X"00000000000000000000000000000000"
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 47                                       & X"00000000000000000000000000000000";
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 48                 INIT_07 : bit_vector := X"00000000000000000000000000000000"
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 49                                       & X"00000000000000000000000000000000";
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 50                 INIT_08 : bit_vector := X"00000000000000000000000000000000"
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 51                                       & X"00000000000000000000000000000000";
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 52                 INIT_09 : bit_vector := X"00000000000000000000000000000000"
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 53                                       & X"00000000000000000000000000000000";
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 54                 INIT_0A : bit_vector := X"00000000000000000000000000000000"
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 55                                       & X"00000000000000000000000000000000";
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 56                 INIT_0B : bit_vector := X"00000000000000000000000000000000"
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 57                                       & X"00000000000000000000000000000000";
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 58                 INIT_0C : bit_vector := X"00000000000000000000000000000000"
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 59                                       & X"00000000000000000000000000000000";
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 60                 INIT_0D : bit_vector := X"00000000000000000000000000000000"
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 61                                       & X"00000000000000000000000000000000";
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 62                 INIT_0E : bit_vector := X"00000000000000000000000000000000"
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 63                                       & X"00000000000000000000000000000000";
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 64                 INIT_0F : bit_vector := X"00000000000000000000000000000000"
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 65                                       & X"00000000000000000000000000000000");
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 66
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 67         port(   ADDRA   : in  std_logic_vector(9 downto 0);
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 68                 ADDRB   : in  std_logic_vector(9 downto 0);
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 69                 CLKA    : in  std_ulogic;
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 70                 CLKB    : in  std_ulogic;
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 71                 DIA     : in  std_logic_vector(3 downto 0);
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 72                 DIB     : in  std_logic_vector(3 downto 0);
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 73                 ENA     : in  std_ulogic;
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 74                 ENB     : in  std_ulogic;
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 75                 RSTA    : in  std_ulogic;
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 76                 RSTB    : in  std_ulogic;
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 77                 WEA     : in  std_ulogic;
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 78                 WEB     : in  std_ulogic;
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 79
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 80                 DOA     : out std_logic_vector(3 downto 0);
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 81                 DOB     : out std_logic_vector(3 downto 0));
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 82     end RAMB4_S4_S4;
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 83
100 
 84     architecture Behavioral of RAMB4_S4_S4 is
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 85
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 86     function cv(A : bit) return std_logic is
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 87     begin
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 88        if (A = '1') then return '1';
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 89        else              return '0';
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 90        end if;
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 91     end;
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 92
109 
 93     function cv1(A : std_logic) return bit is
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 94     begin
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 95        if (A = '1') then return '1';
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 96        else              return '0';
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 97        end if;
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 98     end;
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 99
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100     signal DATA : bit_vector(4095 downto 0) :=
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101         INIT_0F & INIT_0E & INIT_0D & INIT_0C & INIT_0B & INIT_0A & INIT_09 & INIT_08 &
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102         INIT_07 & INIT_06 & INIT_05 & INIT_04 & INIT_03 & INIT_02 & INIT_01 & INIT_00;
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103
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104     begin
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105
122 
106         process(CLKA, CLKB)
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107         begin
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108             if (rising_edge(CLKA)) then
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109                 if (ENA = '1') then
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110                     DOA(3) <= cv(DATA(conv_integer(ADDRA & "11")));
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111                     DOA(2) <= cv(DATA(conv_integer(ADDRA & "10")));
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112                     DOA(1) <= cv(DATA(conv_integer(ADDRA & "01")));
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113                     DOA(0) <= cv(DATA(conv_integer(ADDRA & "00")));
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114                     if (WEA = '1') then
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115                         DATA(conv_integer(ADDRA & "11")) <= cv1(DIA(3));
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116                         DATA(conv_integer(ADDRA & "10")) <= cv1(DIA(2));
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117                         DATA(conv_integer(ADDRA & "01")) <= cv1(DIA(1));
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118                         DATA(conv_integer(ADDRA & "00")) <= cv1(DIA(0));
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119                     end if;
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120                end if;
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121             end if;
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122
139 
123             if (rising_edge(CLKB)) then
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124                 if (ENB = '1') then
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125                     DOB(3) <= cv(DATA(conv_integer(ADDRB & "11")));
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126                     DOB(2) <= cv(DATA(conv_integer(ADDRB & "10")));
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127                     DOB(1) <= cv(DATA(conv_integer(ADDRB & "01")));
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128                     DOB(0) <= cv(DATA(conv_integer(ADDRB & "00")));
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129                     if (WEB = '1') then
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130                         DATA(conv_integer(ADDRB & "11")) <= cv1(DIB(3));
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131                         DATA(conv_integer(ADDRB & "10")) <= cv1(DIB(2));
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132                         DATA(conv_integer(ADDRB & "01")) <= cv1(DIB(1));
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133                         DATA(conv_integer(ADDRB & "00")) <= cv1(DIB(0));
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134                     end if;
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135                 end if;
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136             end if;
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137         end process;
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138
155 
139     end Behavioral;
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140
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<pre class="filename">
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test/RAMB4_S4_S4.vhd
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</pre></pre>
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