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[/] [cpu_lecture/] [trunk/] [src/] [common.vhd] - Blame information for rev 17

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1 2 jsauermann
-------------------------------------------------------------------------------
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-- 
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-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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-- 
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--  This code is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This code is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this code (see the file named COPYING).
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--  If not, see http://www.gnu.org/licenses/.
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--  
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-- Module Name:    common
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-- Create Date:    13:51:24 11/07/2009 
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-- Description:    constants shared by different modules.
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--
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-------------------------------------------------------------------------------
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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package common is
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    -----------------------------------------------------------------------
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    -- ALU operations
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    --
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    constant ALU_ADC    : std_logic_vector(4 downto 0) := "00000";
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    constant ALU_ADD    : std_logic_vector(4 downto 0) := "00001";
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    constant ALU_ADIW   : std_logic_vector(4 downto 0) := "00010";
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    constant ALU_AND    : std_logic_vector(4 downto 0) := "00011";
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    constant ALU_ASR    : std_logic_vector(4 downto 0) := "00100";
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    constant ALU_BLD    : std_logic_vector(4 downto 0) := "00101";
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    constant ALU_BIT_CS : std_logic_vector(4 downto 0) := "00110";
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    constant ALU_COM    : std_logic_vector(4 downto 0) := "00111";
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    constant ALU_DEC    : std_logic_vector(4 downto 0) := "01000";
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    constant ALU_EOR    : std_logic_vector(4 downto 0) := "01001";
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    constant ALU_MV_16  : std_logic_vector(4 downto 0) := "01010";
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    constant ALU_INC    : std_logic_vector(4 downto 0) := "01011";
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    constant ALU_INTR   : std_logic_vector(4 downto 0) := "01100";
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    constant ALU_LSR    : std_logic_vector(4 downto 0) := "01101";
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    constant ALU_D_MV_Q : std_logic_vector(4 downto 0) := "01110";
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    constant ALU_R_MV_Q : std_logic_vector(4 downto 0) := "01111";
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    constant ALU_MULT   : std_logic_vector(4 downto 0) := "10000";
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    constant ALU_NEG    : std_logic_vector(4 downto 0) := "10001";
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    constant ALU_OR     : std_logic_vector(4 downto 0) := "10010";
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    constant ALU_PC_1   : std_logic_vector(4 downto 0) := "10011";
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    constant ALU_PC_2   : std_logic_vector(4 downto 0) := "10100";
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    constant ALU_ROR    : std_logic_vector(4 downto 0) := "10101";
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    constant ALU_SBC    : std_logic_vector(4 downto 0) := "10110";
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    constant ALU_SBIW   : std_logic_vector(4 downto 0) := "10111";
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    constant ALU_SREG   : std_logic_vector(4 downto 0) := "11000";
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    constant ALU_SUB    : std_logic_vector(4 downto 0) := "11001";
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    constant ALU_SWAP   : std_logic_vector(4 downto 0) := "11010";
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    -----------------------------------------------------------------------
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    --
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    -- PC manipulations
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    --
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    constant PC_NEXT    : std_logic_vector(2 downto 0) := "000";    -- PC += 1
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    constant PC_BCC     : std_logic_vector(2 downto 0) := "001";    -- PC ?= IMM
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    constant PC_LD_I    : std_logic_vector(2 downto 0) := "010";    -- PC = IMM
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    constant PC_LD_Z    : std_logic_vector(2 downto 0) := "011";    -- PC = Z
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    constant PC_LD_S    : std_logic_vector(2 downto 0) := "100";    -- PC = (SP)
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    constant PC_SKIP_Z  : std_logic_vector(2 downto 0) := "101";    -- SKIP if Z
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    constant PC_SKIP_T  : std_logic_vector(2 downto 0) := "110";    -- SKIP if T
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    -----------------------------------------------------------------------
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    --
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    -- Addressing modes. An address mode consists of two sub-fields,
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    -- which are the source of the address and an offset from the source.
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    -- Bit 3 indicates if the address will be modified.
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    -- address source
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    constant AS_SP  : std_logic_vector(2 downto 0) := "000";     -- SP
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    constant AS_Z   : std_logic_vector(2 downto 0) := "001";     -- Z
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    constant AS_Y   : std_logic_vector(2 downto 0) := "010";     -- Y
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    constant AS_X   : std_logic_vector(2 downto 0) := "011";     -- X
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    constant AS_IMM : std_logic_vector(2 downto 0) := "100";     -- IMM
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    -- address offset
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    constant AO_0   : std_logic_vector(5 downto 3) := "000";     -- as is
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    constant AO_Q   : std_logic_vector(5 downto 3) := "010";     -- +q
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    constant AO_i   : std_logic_vector(5 downto 3) := "001";     -- +1
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    constant AO_ii  : std_logic_vector(5 downto 3) := "011";     -- +2
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    constant AO_d   : std_logic_vector(5 downto 3) := "101";     -- -1
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    constant AO_dd  : std_logic_vector(5 downto 3) := "111";     -- -2
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    --                                                   |
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    --                                                +--+
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    -- address updated ?                              |
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    --                                                v
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    constant AM_WX : std_logic_vector(3 downto 0) := '1' & AS_X;  -- X ++ or --
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    constant AM_WY : std_logic_vector(3 downto 0) := '1' & AS_Y;  -- Y ++ or --
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    constant AM_WZ : std_logic_vector(3 downto 0) := '1' & AS_Z;  -- Z ++ or --
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    constant AM_WS : std_logic_vector(3 downto 0) := '1' & AS_SP; -- SP ++/--
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    -- address modes used
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    --
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    constant AMOD_ABS : std_logic_vector(5 downto 0) := AO_0  & AS_IMM; -- IMM
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    constant AMOD_X   : std_logic_vector(5 downto 0) := AO_0  & AS_X;   -- X
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    constant AMOD_Xq  : std_logic_vector(5 downto 0) := AO_Q  & AS_X;   -- X+q
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    constant AMOD_Xi  : std_logic_vector(5 downto 0) := AO_i  & AS_X;   -- X+
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    constant AMOD_dX  : std_logic_vector(5 downto 0) := AO_d  & AS_X;   -- -X
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    constant AMOD_Y   : std_logic_vector(5 downto 0) := AO_0  & AS_Y;   -- Y
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    constant AMOD_Yq  : std_logic_vector(5 downto 0) := AO_Q  & AS_Y;   -- Y+q
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    constant AMOD_Yi  : std_logic_vector(5 downto 0) := AO_i  & AS_Y;   -- Y+
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    constant AMOD_dY  : std_logic_vector(5 downto 0) := AO_d  & AS_Y;   -- -Y
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    constant AMOD_Z   : std_logic_vector(5 downto 0) := AO_0  & AS_Z;   -- Z
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    constant AMOD_Zq  : std_logic_vector(5 downto 0) := AO_Q  & AS_Z;   -- Z+q
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    constant AMOD_Zi  : std_logic_vector(5 downto 0) := AO_i  & AS_Z;   -- Z+
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    constant AMOD_dZ  : std_logic_vector(5 downto 0) := AO_d  & AS_Z;   -- -Z
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    constant AMOD_iSP : std_logic_vector(5 downto 0) := AO_i  & AS_SP;  -- +SP
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    constant AMOD_iiSP: std_logic_vector(5 downto 0) := AO_ii & AS_SP;  -- ++SP
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    constant AMOD_SPd : std_logic_vector(5 downto 0) := AO_d  & AS_SP;  -- SP-
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    constant AMOD_SPdd: std_logic_vector(5 downto 0) := AO_dd & AS_SP;  -- SP--
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    -----------------------------------------------------------------------
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    --
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    -- ALU multiplexers.
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    --
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    constant RS_REG : std_logic_vector(1 downto 0) := "00";
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    constant RS_IMM : std_logic_vector(1 downto 0) := "01";
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    constant RS_DIN : std_logic_vector(1 downto 0) := "10";
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    -----------------------------------------------------------------------
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    --
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    -- Multiplier variants. F means FMULT (as opposed to MULT).
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    -- S and U means signed vs. unsigned operands.
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    --
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    constant MULT_UU  : std_logic_vector(2 downto 0) := "000";
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    constant MULT_SU  : std_logic_vector(2 downto 0) := "010";
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    constant MULT_SS  : std_logic_vector(2 downto 0) := "011";
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    constant MULT_FUU : std_logic_vector(2 downto 0) := "100";
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    constant MULT_FSU : std_logic_vector(2 downto 0) := "110";
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    constant MULT_FSS : std_logic_vector(2 downto 0) := "111";
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    -----------------------------------------------------------------------
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end common;
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