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[/] [cpu_lecture/] [trunk/] [src/] [io.vhd] - Blame information for rev 22

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1 2 jsauermann
-------------------------------------------------------------------------------
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-- 
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-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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-- 
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--  This code is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This code is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this code (see the file named COPYING).
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--  If not, see http://www.gnu.org/licenses/.
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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-- Module Name:    io - Behavioral 
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-- Create Date:    13:59:36 11/07/2009 
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-- Description:    the I/O of a CPU (uart and general purpose I/O lines).
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--
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-------------------------------------------------------------------------------
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity io is
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    port (  I_CLK       : in  std_logic;
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            I_CLR       : in  std_logic;
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            I_ADR_IO    : in  std_logic_vector( 7 downto 0);
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            I_DIN       : in  std_logic_vector( 7 downto 0);
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            I_SWITCH    : in  std_logic_vector( 7 downto 0);
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            I_RD_IO     : in  std_logic;
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            I_RX        : in  std_logic;
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            I_WE_IO     : in  std_logic;
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            Q_7_SEGMENT : out std_logic_vector( 6 downto 0);
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            Q_DOUT      : out std_logic_vector( 7 downto 0);
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            Q_INTVEC    : out std_logic_vector( 5 downto 0);
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            Q_LEDS      : out std_logic_vector( 1 downto 0);
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            Q_TX        : out std_logic);
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end io;
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architecture Behavioral of io is
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component uart
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    generic(CLOCK_FREQ  : std_logic_vector(31 downto 0);
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            BAUD_RATE   : std_logic_vector(27 downto 0));
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    port(   I_CLK       : in  std_logic;
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            I_CLR       : in  std_logic;
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            I_RD        : in  std_logic;
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            I_WE        : in  std_logic;
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            I_RX        : in  std_logic;
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            I_TX_DATA   : in  std_logic_vector(7 downto 0);
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            Q_RX_DATA   : out std_logic_vector(7 downto 0);
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            Q_RX_READY  : out std_logic;
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            Q_TX        : out std_logic;
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            Q_TX_BUSY   : out std_logic);
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end component;
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signal U_RX_READY       : std_logic;
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signal U_TX_BUSY        : std_logic;
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signal U_RX_DATA        : std_logic_vector( 7 downto 0);
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signal L_INTVEC         : std_logic_vector( 5 downto 0);
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signal L_LEDS           : std_logic;
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signal L_RD_UART        : std_logic;
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signal L_RX_INT_ENABLED : std_logic;
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signal L_TX_INT_ENABLED : std_logic;
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signal L_WE_UART        : std_logic;
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begin
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    urt: uart
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    generic map(CLOCK_FREQ  => std_logic_vector(conv_unsigned(25000000, 32)),
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                BAUD_RATE   => std_logic_vector(conv_unsigned(   38400, 28)))
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    port map(   I_CLK      => I_CLK,
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                I_CLR      => I_CLR,
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                I_RD       => L_RD_UART,
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                I_WE       => L_WE_UART,
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                I_TX_DATA  => I_DIN(7 downto 0),
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                I_RX       => I_RX,
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                Q_TX       => Q_TX,
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                Q_RX_DATA  => U_RX_DATA,
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                Q_RX_READY => U_RX_READY,
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                Q_TX_BUSY  => U_TX_BUSY);
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    -- IO read process
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    --
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    iord: process(I_ADR_IO, I_SWITCH,
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                  U_RX_DATA, U_RX_READY, L_RX_INT_ENABLED,
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                  U_TX_BUSY, L_TX_INT_ENABLED)
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    begin
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        -- addresses for mega8 device (use iom8.h or #define __AVR_ATmega8__).
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        --
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        case I_ADR_IO is
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            when X"2A"  => Q_DOUT <=             -- UCSRB:
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                               L_RX_INT_ENABLED  -- Rx complete int enabled.
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                             & L_TX_INT_ENABLED  -- Tx complete int enabled.
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                             & L_TX_INT_ENABLED  -- Tx empty int enabled.
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                             & '1'               -- Rx enabled
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                             & '1'               -- Tx enabled
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                             & '0'               -- 8 bits/char
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                             & '0'               -- Rx bit 8
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                             & '0';              -- Tx bit 8
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            when X"2B"  => Q_DOUT <=             -- UCSRA:
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                               U_RX_READY       -- Rx complete
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                             & not U_TX_BUSY    -- Tx complete
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                             & not U_TX_BUSY    -- Tx ready
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                             & '0'              -- frame error
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                             & '0'              -- data overrun
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                             & '0'              -- parity error
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                             & '0'              -- double dpeed
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                             & '0';             -- multiproc mode
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            when X"2C"  => Q_DOUT <= U_RX_DATA; -- UDR
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            when X"40"  => Q_DOUT <=            -- UCSRC
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                               '1'              -- URSEL
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                             & '0'              -- asynchronous
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                             & "00"             -- no parity
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                             & '1'              -- two stop bits
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                             & "11"             -- 8 bits/char
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                             & '0';             -- rising clock edge
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            when X"36"  => Q_DOUT <= I_SWITCH;  -- PINB
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            when others => Q_DOUT <= X"AA";
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        end case;
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    end process;
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    -- IO write process
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    --
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    iowr: process(I_CLK)
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    begin
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        if (rising_edge(I_CLK)) then
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            if (I_CLR = '1') then
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                L_RX_INT_ENABLED  <= '0';
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                L_TX_INT_ENABLED  <= '0';
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            elsif (I_WE_IO = '1') then
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                case I_ADR_IO is
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                    when X"38"  => -- PORTB
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                                   Q_7_SEGMENT <= I_DIN(6 downto 0);
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                                   L_LEDS <= not L_LEDS;
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                    when X"2A"  => -- UCSRB
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                                   L_RX_INT_ENABLED <= I_DIN(7);
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                                   L_TX_INT_ENABLED <= I_DIN(6);
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                    when X"2B"  => -- UCSRA:       handled by uart
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                    when X"2C"  => -- UDR:         handled by uart
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                    when X"40"  => -- UCSRC/UBRRH: (ignored)
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                    when others =>
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                end case;
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            end if;
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        end if;
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    end process;
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    -- interrupt process
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    --
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    ioint: process(I_CLK)
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    begin
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        if (rising_edge(I_CLK)) then
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            if (I_CLR = '1') then
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                L_INTVEC <= "000000";
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            else
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                if (L_RX_INT_ENABLED and U_RX_READY) = '1' then
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                    if (L_INTVEC(5) = '0') then     -- no interrupt pending
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                        L_INTVEC <= "101011";       -- _VECTOR(11)
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                    end if;
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                elsif (L_TX_INT_ENABLED and not U_TX_BUSY) = '1' then
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                    if (L_INTVEC(5) = '0') then     -- no interrupt pending
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                        L_INTVEC <= "101100";       -- _VECTOR(12)
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                    end if;
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                else                                -- no interrupt
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                    L_INTVEC <= "000000";
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                end if;
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            end if;
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        end if;
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    end process;
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    L_WE_UART <= I_WE_IO when (I_ADR_IO = X"2C") else '0'; -- write UART UDR
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    L_RD_UART <= I_RD_IO when (I_ADR_IO = X"2C") else '0'; -- read  UART UDR
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    Q_LEDS(1) <= L_LEDS;
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    Q_LEDS(0) <= not L_LEDS;
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    Q_INTVEC  <= L_INTVEC;
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end Behavioral;
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