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[/] [cpu_lecture/] [trunk/] [src/] [status_reg.vhd] - Blame information for rev 2

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1 2 jsauermann
-------------------------------------------------------------------------------
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-- 
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-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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-- 
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--  This code is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This code is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this code (see the file named COPYING).
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--  If not, see http://www.gnu.org/licenses/.
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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-- Module Name:    Register - Behavioral 
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-- Create Date:    16:15:54 12/26/2009 
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-- Description:    the status register of a CPU.
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity status_reg is
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    port (  I_CLK       : in  std_logic;
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            I_COND      : in  std_logic_vector ( 3 downto 0);
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            I_DIN       : in  std_logic_vector ( 7 downto 0);
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            I_FLAGS     : in  std_logic_vector ( 7 downto 0);
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            I_WE_F      : in  std_logic;
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            I_WE_SR     : in  std_logic;
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            Q           : out std_logic_vector ( 7 downto 0);
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            Q_CC        : out std_logic);
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end status_reg;
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architecture Behavioral of status_reg is
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signal L                : std_logic_vector ( 7 downto 0);
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begin
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    process(I_CLK)
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    begin
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        if (rising_edge(I_CLK)) then
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            if (I_WE_F = '1') then          -- write flags (from ALU)
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                L <= I_FLAGS;
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            elsif (I_WE_SR = '1') then      -- write I/O
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                L <= I_DIN;
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            end if;
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        end if;
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    end process;
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    cond: process(I_COND, L)
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    begin
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        case I_COND(2 downto 0) is
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            when "000"  => Q_CC <= L(0) xor I_COND(3);
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            when "001"  => Q_CC <= L(1) xor I_COND(3);
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            when "010"  => Q_CC <= L(2) xor I_COND(3);
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            when "011"  => Q_CC <= L(3) xor I_COND(3);
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            when "100"  => Q_CC <= L(4) xor I_COND(3);
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            when "101"  => Q_CC <= L(5) xor I_COND(3);
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            when "110"  => Q_CC <= L(6) xor I_COND(3);
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            when others => Q_CC <= L(7) xor I_COND(3);
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        end case;
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    end process;
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    Q <= L;
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end Behavioral;
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