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[/] [cxd9731/] [D_RAM.v] - Blame information for rev 5

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:31:51 12/08/2008 
// Design Name: 
// Module Name:    DMA_RAM - Behavioral 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
 
 
module D_RAM(
        input CLK4      ,
        input DMA_ARM   ,
        input PS2WrIDE  ,                       // High if PS2 DMA write to IDE bus
//// =====
        input CRC_ARM ,
        input CRC_ENB   ,                       // the enable for the CRC circuit
        output [15:0] CRC_Q ,
//// =====
        output [3:0] BufSize ,           // data size in 512 bytes ready
        output BufEmpty ,               // set when no words in the FIFO buffer
//// =====
        input [15:0] DInA        ,
        output [15:0] DOutA ,
        input [31:0] DInB ,
        output [31:0] DOutB ,
//// =====
        output PA_HvSpace       ,
        output PA_OD_Rdy        ,               // some data availabe for output from Port A
        output PA_AlmostFull ,  // set when buffer has only 4 words left
        output PA_Empty,                        // set when buffer is all drained
        output PA_Full,                 // Register is full.
        output WithinABlock ,
        output reg A0,                                  // A0 to put signal to IDE_DMA
        input   HWOE,                                   // select high order word to output
        input   RegEA,
        input IncAddrA ,
        input EnbA ,                                    // enable and the control signal
        input WrA       ,
//// =====
        output PB_HvSpace       ,
        output PB_OD_Rdy        ,       // some data availabe for output from Port B
        output WithinBBlock ,           // high if (AddrB[6] | AddrB[5]) = 1
        output BBurstEnd        ,               // high if AddrB = xxxx11111 = 1F
        input IncAddrB ,
        input RegEB     ,
        input EnbB      ,
        input WrB
);
 
 
//////////////////////////////////////////////////////
wire    R0Enb,R1Enb,R0Wr,R1Wr,RegEA0,RegEA1;
wire    [15:0] DOutA0,DOutA1,DInBL,DInBH,DOutBL,DOutBH;
reg     [9:0] AddrA,AddrB;
reg     [3:0] Page;
wire    IncPgA,IncPgB;
wire PageNZ,PageZR;
wire HvSpaceA,HvSpaceB;
wire A_Zero,B_Zero;
////-=========================================================================
RAM1 RAM_Lo (
        .clka           (CLK4),
        .dina           (DInA),         // IDE side data bits
        .addra  (AddrA),
        .ena            (R0Enb),
        .wea            (R0Wr),
        .regcea (RegEA0),
        .douta  (DOutA0),
//
        .clkb           (CLK4),
        .dinb           (DInBL),                // PS2 side data bus
        .addrb  (AddrB),
        .enb            (EnbB),
        .regceb (RegEB),
        .web            (WrB),
        .doutb  (DOutBL)
);
//// =========================================
RAM1 RAM_Hi(
        .clka           (CLK4),
        .dina           (DInA),         // IDE side data bits
        .addra  (AddrA),
        .ena            (R1Enb),
        .wea            (R1Wr),
        .regcea (RegEA1),
        .douta  (DOutA1),
//
        .clkb           (CLK4),
        .dinb           (DInBH),                // PS2 side data bus
        .addrb  (AddrB),
        .enb            (EnbB),
        .regceb (RegEB),
        .web            (WrB),
        .doutb  (DOutBH)
);
//// =========================================
 
CRC_CAL CRC(
        .CLK4           (CLK4),                 // same as RAM clock
        .D                      (DInA),                 //- same as the RAM data
        .CRC_ARM        (CRC_ARM),                      //- from the controller unit
        .CRC_ENB        (CRC_ENB),
        .CRC_Q  (CRC_Q)
);
//-=============================================================================
 
//-==== Connect the RAM
assign DOutA[15:0]       = (HWOE == 1'b1) ? DOutA1[15:0] : DOutA0[15:0];
assign DOutB[31:16]     = DOutBH[15:0];
assign DOutB[15:0]       = DOutBL[15:0];
assign DInBH[15:0]       = DInB[31:16];
assign DInBL[15:0]       = DInB[15:0];
assign R0Enb    = EnbA & ~A0;
assign R1Enb    = EnbA &  A0;
assign R0Wr             = WrA  & ~A0;
assign R1Wr             = WrA  &  A0;
assign RegEA0   = RegEA & ~A0;
assign RegEA1   = RegEA &  A0;
////
//// = the page counter ////
assign IncPgA   = IncAddrA & AddrA[6] & AddrA[5] & AddrA[4] & AddrA[3] & AddrA[2] & AddrA[1] & AddrA[0] & A0;
assign IncPgB   = IncAddrB & AddrB[6] & AddrB[5] & AddrB[4] & AddrB[3] & AddrB[2] & AddrB[1] & AddrB[0];
assign BufEmpty = PageZR & A_Zero & B_Zero;
////////-=======================================================
assign HvSpaceA = ~Page[3] & ( ~(Page[2] & Page[1] & Page[0]) | A_Zero );
assign HvSpaceB = ~Page[3] & ( ~(Page[2] & Page[1] & Page[0]) | B_Zero );
assign PageNZ   = Page[3] | Page[2] | Page[1] | Page[0];
assign PageZR   = ~(Page[3] | Page[2] | Page[1] | Page[0]);
assign A_Zero   = ~(AddrA[6] | AddrA[5] | AddrA[4] | AddrA[3] | AddrA[2] | AddrA[1] | AddrA[0]);
assign PA_Empty = PageZR & A_Zero & ~A0;
assign B_Zero   = ~(AddrB[6] | AddrB[5] | AddrB[4] | AddrB[3] | AddrB[2] | AddrB[1] | AddrB[0]);
 
assign PA_OD_Rdy                = PageNZ;
assign PA_HvSpace               = HvSpaceA;             // have 512 byte space at least
assign PA_AlmostFull    = Page[3] | (Page[2] & Page[1] & Page[0] & AddrA[6] & AddrA[5] & AddrA[4] & AddrA[3]);
// PA_Full - a signal set high to indicate all buffer area is used up and until clear one page, should
// not start DMA read into Port A
//  This signal will be high if incremented and will keep high until PortB dec it
assign PA_Full                  = Page[3];
 
assign WithinABlock     = AddrA[6] | AddrA[5] | AddrA[4] | AddrA[3] | AddrA[2] | AddrA[1] | AddrA[0] | A0;
////
assign PB_OD_Rdy                = PageNZ;                       // if there is more than one page of data
assign PB_HvSpace               = HvSpaceB;             // if there is space in buffer
assign WithinBBlock     = AddrB[6] | AddrB[5] | AddrB[4] | AddrB[3] | AddrB[2] | AddrB[1] | AddrB[0];
assign BBurstEnd                = AddrB[4] & AddrB[3] & AddrB[2] & AddrB[1] & AddrB[0]; // high if AddrB = xxxx11111 = 1F
////////
assign BufSize[3:0]      = Page[3:0];
 
////- ============================================================================
always @(posedge CLK4) begin
        if (DMA_ARM == 1'b0)
          AddrB         <=  10'b00_0000_0000;
        else
                if(IncAddrB == 1'b1)
                  AddrB         <= AddrB + 1;
end
 
always @(posedge CLK4) begin
        if (DMA_ARM == 1'b0) begin
          AddrA <=      10'b00_0000_0000;
          A0            <= 1'b0;
        end else begin
                if(IncAddrA == 1'b1) begin
                        if (A0 == 1'b1) begin
                                AddrA   <= AddrA + 1;
                                A0              <= 1'b0;
                        end else begin
                                A0              <= 1'b1;
                        end
                end
        end
end
 
always @(posedge CLK4) begin
        if (DMA_ARM == 1'b0) begin
          Page          <=  4'b0000;
        end else begin
                if (PS2WrIDE == 1'b1) begin     // PS2 writes to drive
                        if (IncPgB == 1'b1) begin
                                if (IncPgA == 1'b0) Page <= Page + 1;   // buffer increase in size
                        end else begin
                                if (IncPgA == 1'b1) Page <= Page - 1;   // buffer decrease in size
                        end
                end else begin
                        if (IncPgA == 1'b1) begin
                                if (IncPgB == 1'b0) Page <= Page + 1;   // buffer has increase in size
                        end else begin
                                if (IncPgB == 1'b1) Page <= Page - 1; // buffer decrease in size
                        end
                end // PS2WrIDE
        end // DMA_ARM
end // always
 
endmodule

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Subversion Repositories cxd9731

[/] [cxd9731/] [D_RAM.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	regttycomi	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company:`
4			`// Engineer:`
5			`//`
6			`// Create Date: 10:31:51 12/08/2008`
7			`// Design Name:`
8			`// Module Name: DMA_RAM - Behavioral`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21
22
23			`module D_RAM(`
24			`input CLK4 ,`
25			`input DMA_ARM ,`
26			`input PS2WrIDE , // High if PS2 DMA write to IDE bus`
27			`//// =====`
28			`input CRC_ARM ,`
29			`input CRC_ENB , // the enable for the CRC circuit`
30			`output [15:0] CRC_Q ,`
31			`//// =====`
32			`output [3:0] BufSize , // data size in 512 bytes ready`
33			`output BufEmpty , // set when no words in the FIFO buffer`
34			`//// =====`
35			`input [15:0] DInA ,`
36			`output [15:0] DOutA ,`
37			`input [31:0] DInB ,`
38			`output [31:0] DOutB ,`
39			`//// =====`
40			`output PA_HvSpace ,`
41			`output PA_OD_Rdy , // some data availabe for output from Port A`
42			`output PA_AlmostFull , // set when buffer has only 4 words left`
43			`output PA_Empty, // set when buffer is all drained`
44			`output PA_Full, // Register is full.`
45			`output WithinABlock ,`
46			`output reg A0, // A0 to put signal to IDE_DMA`
47			`input HWOE, // select high order word to output`
48			`input RegEA,`
49			`input IncAddrA ,`
50			`input EnbA , // enable and the control signal`
51			`input WrA ,`
52			`//// =====`
53			`output PB_HvSpace ,`
54			`output PB_OD_Rdy , // some data availabe for output from Port B`
55			`output WithinBBlock , // high if (AddrB[6] \| AddrB[5]) = 1`
56			`output BBurstEnd , // high if AddrB = xxxx11111 = 1F`
57			`input IncAddrB ,`
58			`input RegEB ,`
59			`input EnbB ,`
60			`input WrB`
61			`);`
62
63
64			`//////////////////////////////////////////////////////`
65			`wire R0Enb,R1Enb,R0Wr,R1Wr,RegEA0,RegEA1;`
66			`wire [15:0] DOutA0,DOutA1,DInBL,DInBH,DOutBL,DOutBH;`
67			`reg [9:0] AddrA,AddrB;`
68			`reg [3:0] Page;`
69			`wire IncPgA,IncPgB;`
70			`wire PageNZ,PageZR;`
71			`wire HvSpaceA,HvSpaceB;`
72			`wire A_Zero,B_Zero;`
73			`////-=========================================================================`
74			`RAM1 RAM_Lo (`
75			`.clka (CLK4),`
76			`.dina (DInA), // IDE side data bits`
77			`.addra (AddrA),`
78			`.ena (R0Enb),`
79			`.wea (R0Wr),`
80			`.regcea (RegEA0),`
81			`.douta (DOutA0),`
82			`//`
83			`.clkb (CLK4),`
84			`.dinb (DInBL), // PS2 side data bus`
85			`.addrb (AddrB),`
86			`.enb (EnbB),`
87			`.regceb (RegEB),`
88			`.web (WrB),`
89			`.doutb (DOutBL)`
90			`);`
91			`//// =========================================`
92			`RAM1 RAM_Hi(`
93			`.clka (CLK4),`
94			`.dina (DInA), // IDE side data bits`
95			`.addra (AddrA),`
96			`.ena (R1Enb),`
97			`.wea (R1Wr),`
98			`.regcea (RegEA1),`
99			`.douta (DOutA1),`
100			`//`
101			`.clkb (CLK4),`
102			`.dinb (DInBH), // PS2 side data bus`
103			`.addrb (AddrB),`
104			`.enb (EnbB),`
105			`.regceb (RegEB),`
106			`.web (WrB),`
107			`.doutb (DOutBH)`
108			`);`
109			`//// =========================================`
110
111			`CRC_CAL CRC(`
112			`.CLK4 (CLK4), // same as RAM clock`
113			`.D (DInA), //- same as the RAM data`
114			`.CRC_ARM (CRC_ARM), //- from the controller unit`
115			`.CRC_ENB (CRC_ENB),`
116			`.CRC_Q (CRC_Q)`
117			`);`
118			`//-=============================================================================`
119
120			`//-==== Connect the RAM`
121			`assign DOutA[15:0] = (HWOE == 1'b1) ? DOutA1[15:0] : DOutA0[15:0];`
122			`assign DOutB[31:16] = DOutBH[15:0];`
123			`assign DOutB[15:0] = DOutBL[15:0];`
124			`assign DInBH[15:0] = DInB[31:16];`
125			`assign DInBL[15:0] = DInB[15:0];`
126			`assign R0Enb = EnbA & ~A0;`
127			`assign R1Enb = EnbA & A0;`
128			`assign R0Wr = WrA & ~A0;`
129			`assign R1Wr = WrA & A0;`
130			`assign RegEA0 = RegEA & ~A0;`
131			`assign RegEA1 = RegEA & A0;`
132			`////`
133			`//// = the page counter ////`
134			`assign IncPgA = IncAddrA & AddrA[6] & AddrA[5] & AddrA[4] & AddrA[3] & AddrA[2] & AddrA[1] & AddrA[0] & A0;`
135			`assign IncPgB = IncAddrB & AddrB[6] & AddrB[5] & AddrB[4] & AddrB[3] & AddrB[2] & AddrB[1] & AddrB[0];`
136			`assign BufEmpty = PageZR & A_Zero & B_Zero;`
137			`////////-=======================================================`
138			`assign HvSpaceA = ~Page[3] & ( ~(Page[2] & Page[1] & Page[0]) \| A_Zero );`
139			`assign HvSpaceB = ~Page[3] & ( ~(Page[2] & Page[1] & Page[0]) \| B_Zero );`
140			`assign PageNZ = Page[3] \| Page[2] \| Page[1] \| Page[0];`
141			`assign PageZR = ~(Page[3] \| Page[2] \| Page[1] \| Page[0]);`
142			`assign A_Zero = ~(AddrA[6] \| AddrA[5] \| AddrA[4] \| AddrA[3] \| AddrA[2] \| AddrA[1] \| AddrA[0]);`
143			`assign PA_Empty = PageZR & A_Zero & ~A0;`
144			`assign B_Zero = ~(AddrB[6] \| AddrB[5] \| AddrB[4] \| AddrB[3] \| AddrB[2] \| AddrB[1] \| AddrB[0]);`
145
146			`assign PA_OD_Rdy = PageNZ;`
147			`assign PA_HvSpace = HvSpaceA; // have 512 byte space at least`
148			`assign PA_AlmostFull = Page[3] \| (Page[2] & Page[1] & Page[0] & AddrA[6] & AddrA[5] & AddrA[4] & AddrA[3]);`
149			`// PA_Full - a signal set high to indicate all buffer area is used up and until clear one page, should`
150			`// not start DMA read into Port A`
151			`// This signal will be high if incremented and will keep high until PortB dec it`
152			`assign PA_Full = Page[3];`
153
154			`assign WithinABlock = AddrA[6] \| AddrA[5] \| AddrA[4] \| AddrA[3] \| AddrA[2] \| AddrA[1] \| AddrA[0] \| A0;`
155			`////`
156			`assign PB_OD_Rdy = PageNZ; // if there is more than one page of data`
157			`assign PB_HvSpace = HvSpaceB; // if there is space in buffer`
158			`assign WithinBBlock = AddrB[6] \| AddrB[5] \| AddrB[4] \| AddrB[3] \| AddrB[2] \| AddrB[1] \| AddrB[0];`
159			`assign BBurstEnd = AddrB[4] & AddrB[3] & AddrB[2] & AddrB[1] & AddrB[0]; // high if AddrB = xxxx11111 = 1F`
160			`////////`
161			`assign BufSize[3:0] = Page[3:0];`
162
163			`////- ============================================================================`
164			`always @(posedge CLK4) begin`
165			`if (DMA_ARM == 1'b0)`
166			`AddrB <= 10'b00_0000_0000;`
167			`else`
168			`if(IncAddrB == 1'b1)`
169			`AddrB <= AddrB + 1;`
170			`end`
171
172			`always @(posedge CLK4) begin`
173			`if (DMA_ARM == 1'b0) begin`
174			`AddrA <= 10'b00_0000_0000;`
175			`A0 <= 1'b0;`
176			`end else begin`
177			`if(IncAddrA == 1'b1) begin`
178			`if (A0 == 1'b1) begin`
179			`AddrA <= AddrA + 1;`
180			`A0 <= 1'b0;`
181			`end else begin`
182			`A0 <= 1'b1;`
183			`end`
184			`end`
185			`end`
186			`end`
187
188			`always @(posedge CLK4) begin`
189			`if (DMA_ARM == 1'b0) begin`
190			`Page <= 4'b0000;`
191			`end else begin`
192			`if (PS2WrIDE == 1'b1) begin // PS2 writes to drive`
193			`if (IncPgB == 1'b1) begin`
194			`if (IncPgA == 1'b0) Page <= Page + 1; // buffer increase in size`
195			`end else begin`
196			`if (IncPgA == 1'b1) Page <= Page - 1; // buffer decrease in size`
197			`end`
198			`end else begin`
199			`if (IncPgA == 1'b1) begin`
200			`if (IncPgB == 1'b0) Page <= Page + 1; // buffer has increase in size`
201			`end else begin`
202			`if (IncPgB == 1'b1) Page <= Page - 1; // buffer decrease in size`
203			`end`
204			`end // PS2WrIDE`
205			`end // DMA_ARM`
206			`end // always`
207
208			`endmodule`