URL https://opencores.org/ocsvn/darkriscv/darkriscv/trunk

Subversion Repositories darkriscv

[/] [darkriscv/] [trunk/] [rtl/] [README.md] - Blame information for rev 2

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## Verilog Sources
 
Description of current Verilog files:
 
- darkriscv.v: the DarkRISCV core
- darksocv.v: a primitive system on-chip w/ the DarkRISCV core wired to ROM and RAM memories and IO
- darkuart.v: a small full-duplex UART w/ programmable baud-rate
- config.vh: configuration file!
 
TODO:
 
- add a cache controller
- add a SDRAM controller
- add a SPI controller
- add a GbE controller

Line No.	Rev	Author	Line
1	2	marcelos	`## Verilog Sources`
2
3			`Description of current Verilog files:`
4
5			`- darkriscv.v: the DarkRISCV core`
6			`- darksocv.v: a primitive system on-chip w/ the DarkRISCV core wired to ROM and RAM memories and IO`
7			`- darkuart.v: a small full-duplex UART w/ programmable baud-rate`
8			`- config.vh: configuration file!`
9
10			`TODO:`
11
12			`- add a cache controller`
13			`- add a SDRAM controller`
14			`- add a SPI controller`
15			`- add a GbE controller`

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[/] [darkriscv/] [trunk/] [rtl/] [README.md] - Blame information for rev 2