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[/] [ddr3_synthesizable_bfm/] [trunk/] [rtl/] [ddr3_simple4.v] - Blame information for rev 7

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1 2 slai
/*
2
*DDR3 Simple Synthesizable Memory BFM
3
*2010-2011 sclai <laikos@yahoo.com>
4
*
5
*This library is free software; you can redistribute it and/or modify it
6
* under the terms of the GNU Lesser General Public License as published by
7
* the Free Software Foundation; either version 2.1 of the License,
8
* or (at your option) any later version.
9
*
10
* This library is distributed in the hope that it will be useful, but
11
* WITHOUT ANY WARRANTY; without even the implied warranty of
12
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13
* Lesser General Public License for more details.
14
*
15
* You should have received a copy of the GNU Lesser General Public
16
* License along with this library; if not, write to the Free Software
17
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
18
* USA
19
*
20
*
21 3 slai
*  Simple implementation of DDR3 Memory
22 2 slai
*  will only reponse to write and read request
23
*  parameter
24
*  count start from t0,t2,t2...
25
*  ck _|-|_|-|_|-|_|-|_
26
*
27
*  cs#---|___|---------
28
*
29
*        |   |    |
30
*        t0  t1  t2 ....
31
*
32 4 slai
*
33 2 slai
*/
34
 
35
`timescale 1ps / 1ps
36
 
37
module ddr3_simple4#(
38
parameter MEM_DQ_WIDTH          =8,
39
parameter MEM_BA_WIDTH          =3,
40
parameter MEM_ROW_WIDTH         =13,
41
parameter MEM_COL_WIDTH         =13,
42 7 slai
parameter AL            =3,
43
parameter CWL           =5, //CWL
44
parameter CL            =5  //CL=6 -> pass
45 2 slai
)(
46
input wire [MEM_ROW_WIDTH-1:0]   a,
47
input wire [ MEM_BA_WIDTH-1:0]   ba,
48 4 slai
input wire                      ck,
49
input wire                      ck_n,
50
input wire                      cke,
51
input wire                      cs_n,
52
input wire                      dm,
53
input wire                      ras_n,
54
input wire                      cas_n,
55
input wire                      we_n,
56
input wire                      reset_n,
57
inout wire [MEM_DQ_WIDTH-1:0]    dq,
58
inout wire                      dqs,
59
inout wire                      dqs_n,
60
input wire                      odt
61 2 slai
);
62
 
63 4 slai
//convert actual CL and CWL parameter to 
64 7 slai
localparam  MEM_CWL=CWL+AL;
65
localparam  MEM_CL =CL+AL;
66 2 slai
 
67
//definitions
68 4 slai
localparam      OPCODE_PRECHARGE = 4'b0010;
69
localparam      OPCODE_ACTIVATE  = 4'b0011;
70
localparam      OPCODE_WRITE     = 4'b0100;
71
localparam      OPCODE_READ      = 4'b0101;
72
localparam      OPCODE_MRS       = 4'b0000;
73
localparam      OPCODE_REFRESH   = 4'b0001;
74
localparam      OPCODE_DES       = 4'b1000;
75
localparam      OPCODE_ZQC       = 4'b0110;
76
localparam      OPCODE_NOP       = 4'b0111;
77 2 slai
 
78
//mode registers
79
reg [31:0] mr0;
80
reg [31:0] mr2;
81
reg [31:0] mr3;
82
 
83
 
84
wire [35:0] write_add;
85
wire [35:0] read_add;
86
wire [3:0]  write_cmd;
87
wire [3:0]  read_cmd;
88
(* keep *)wire [(MEM_DQ_WIDTH*2)-1:0] read_data;
89
 
90
reg [ 2:0] last_bank;
91
reg [15:0] last_row;
92
reg [3:0] last_write_cmd;
93
reg [3:0] last_read_cmd;
94
reg [35:0] last_write_add;
95
reg [35:0] last_read_add;
96
 
97
reg        write_address12;
98
reg        read_address12;
99
 
100
//bank tracker
101
reg [MEM_ROW_WIDTH-1:0]opened_row[(2**MEM_BA_WIDTH)-1:0];
102
//row  tracker
103
 
104
wire [MEM_DQ_WIDTH-1:0]  dq_out;
105
reg  [MEM_DQ_WIDTH-1:0]  dq_in0;
106
 
107
(* keep *) wire [MEM_DQ_WIDTH-1:0] data_hi;
108
(* keep *) wire [MEM_DQ_WIDTH-1:0] data_lo;
109 4 slai
(* keep *) wire                   data_hi_dm;
110
(* keep *) wire                   data_lo_dm;
111 2 slai
//IDDR
112
my_iddrx8 iddrx8_inst(
113
        .clk(ck),
114
        .io(dq),
115
        .d0(data_lo),
116
        .d1(data_hi)
117
);
118
 
119
my_iddrx8 iddrx8_dm_inst(
120
        .clk(ck),
121
        .io(dm),
122
        .d0(data_lo_dm),
123
        .d1(data_hi_dm)
124
);
125
 
126
//ODDR
127
my_oddrx8 oddrx8_inst(
128
.clk(ck),
129
.d0(read_data[ MEM_DQ_WIDTH-1:0              ]),
130
.d1(read_data[(MEM_DQ_WIDTH*2)-1:MEM_DQ_WIDTH]),
131
.io(dq_out)
132
);
133
 
134
//double data rate
135
always @(posedge ck )
136
begin
137
if(reset_n==1'b0)
138
        begin
139
                last_bank     <=4'h0;
140
                last_row      <=16'h0000;
141
        end
142
else
143
begin
144
        case({cs_n,ras_n,cas_n,we_n})
145
        /*
146
        OPCODE_PRECHARGE        :begin
147 4 slai
                                        $display("t=%d,PRECHARGE",vip_clk);
148
                                end
149 2 slai
        */
150
        OPCODE_ACTIVATE         :begin
151 4 slai
                                        opened_row [ba] <={{(16-MEM_ROW_WIDTH){1'b0}},a[MEM_ROW_WIDTH-1:0]};
152
                                end
153 2 slai
        /*
154 4 slai
        OPCODE_DES              :begin
155
                                        $display("t=%d,DES",vip_clk);
156
                                end
157 2 slai
        OPCODE_MRS              :begin
158 4 slai
                                        $display("t=%d,MRS",vip_clk);
159
                                end
160 2 slai
        OPCODE_NOP              :begin
161 4 slai
                                        //$display("t=%d,NOP",vip_clk);
162
                                end
163 2 slai
        */
164
        OPCODE_READ             :begin
165 4 slai
                                        last_read_add   <={ba,opened_row[ba],{{(16-MEM_COL_WIDTH){1'b0}},a[MEM_COL_WIDTH-1:0]}};
166
                                        last_read_cmd   <=OPCODE_READ;
167
                                end
168 2 slai
        OPCODE_WRITE            :begin
169 4 slai
                                        last_write_add  <={ba,opened_row[ba],{{(16-MEM_COL_WIDTH){1'b0}},a[MEM_COL_WIDTH-1:0]}};
170
                                        last_write_cmd  <=OPCODE_WRITE;
171
                                end
172 2 slai
                                                        /*
173 4 slai
        OPCODE_ZQC              :begin
174
                                $display("t=%d,ZQC",vip_clk);
175
                                        end*/
176 2 slai
                default:begin
177
                                last_read_cmd   <=OPCODE_NOP;
178
                                last_write_cmd <=OPCODE_NOP;
179 4 slai
                        end
180 2 slai
        endcase
181
end // end reset        
182
end // end always@(*)
183
 
184
 
185
 
186
//cmd
187
//read
188
ddr3_sr4 #(
189 4 slai
.PIPE_LEN(MEM_CL)
190 2 slai
)ddr3_read_cmd_sr(
191
        .clk(ck),
192
        .shift_in(last_read_cmd),
193
        .shift_out(read_cmd)
194
);
195
//bank, row, col
196
ddr3_sr36 #(
197 4 slai
.PIPE_LEN(MEM_CL+1)
198 2 slai
)ddr3_read_add_sr(
199
        .clk(ck),
200
        .shift_in(last_read_add),
201
        .shift_out(read_add)
202
);
203
 
204
//cmd
205
//write
206
ddr3_sr4#(
207 4 slai
.PIPE_LEN(MEM_CWL)
208 2 slai
)ddr3_write_cmd_sr(
209
        .clk(ck),
210
        .shift_in(last_write_cmd),
211
        .shift_out(write_cmd)
212
);
213
 
214
//bank, row, col
215
ddr3_sr36#(
216 4 slai
.PIPE_LEN(MEM_CWL+1) //have to be a cycle late to wait for IDDR latency
217 2 slai
) ddr3_write_add_sr(
218
        .clk(ck),
219
        .shift_in(last_write_add),
220
        .shift_out(write_add)
221
);
222
 
223
 
224
//write fsm
225
localparam WR_D0        =4'd0;
226
localparam WR_D1        =4'd1;
227
localparam WR_D2        =4'd2;
228 4 slai
localparam WR_D3        =4'd3;
229
localparam WR_IDLE      =4'd5;
230 2 slai
reg [3:0] write_state;
231
reg              mem_we;
232
reg [2:0] write_col;
233
always@(posedge ck)
234
begin
235
        if(reset_n==1'b0)
236
                begin
237
                        write_state<=WR_IDLE;
238
                        mem_we<=1'b0;
239
                        write_col<=0;
240
                end
241
        else
242
                begin
243
                case(write_state)
244
                        WR_IDLE:begin
245
                        write_col<=0;
246
                        if(write_cmd==OPCODE_WRITE)
247
                                begin
248
                                        write_state<=WR_D0;
249
                                        mem_we<=1'b1;
250
                                end
251
                        else
252
                                begin
253
                                        write_state<=WR_IDLE;
254
                                        mem_we<=1'b0;
255
                                end
256
                        end
257
                        WR_D0:begin
258
                                write_address12<=write_add[12];
259
                                write_state<=WR_D1;
260
                                write_col<=write_col+1'b1;
261
                                $display("%m: at time %t\tWRITE BANK[%x]\tROW[%x]\tCOL[%x]\tWR D0: %x-%x",$time,write_add[34:32],write_add[31:16],write_add[15:0],data_hi,data_lo);
262
                        end
263
                        WR_D1:begin
264
                                if(write_address12==1'b1)
265
                                        begin
266
                                                write_state<=WR_D2;
267
                                                write_col<=write_col+1'b1;
268
                                        end
269
                                else if (write_cmd==OPCODE_WRITE)
270
                                        begin
271
                                                write_state<=WR_D0;
272
                                                write_col<=0;
273
                                        end
274
                                else
275
                                        begin
276
                                                write_state<=WR_IDLE;
277
                                                mem_we<=1'b0;
278
                                        end
279
                                $display("%m: at time %t\tWRITE BANK[%x]\tROW[%x]\tCOL[%x]\tWR D1: %x-%x",$time,write_add[34:32],write_add[31:16],write_add[15:0],data_hi,data_lo);
280
                        end
281
                        WR_D2:begin
282
                                write_state<=WR_D3;
283
                                write_col<=write_col+1'b1;
284
                                $display("%m: at time %t\tWRITE BANK[%x]\tROW[%x]\tCOL[%x]\tWR D2: %x-%x",$time,write_add[34:32],write_add[31:16],write_add[15:0],data_hi,data_lo);
285
                        end
286
                        WR_D3:begin
287
                                $display("%m: at time %t\tWRITE BANK[%x]\tROW[%x]\tCOL[%x]\tWR D3: %x-%x",$time,write_add[34:32],write_add[31:16],write_add[15:0],data_hi,data_lo);
288
 
289
                                //write_col<=write_col+1'b1;    
290
                                if (write_cmd==OPCODE_WRITE)
291
                                        begin
292
                                                write_state<=WR_D0;
293
                                                write_col<=0;
294
                                        end
295
                                else
296
                                        begin
297
                                                write_state<=WR_IDLE;
298
                                                mem_we<=1'b0;
299
                                        end
300
                        end
301
                endcase
302
                end //endif
303
end
304
 
305
 
306
//read fsm
307
localparam RD_D0        =4'd0;
308
localparam RD_D1        =4'd1;
309
localparam RD_D2        =4'd2;
310 4 slai
localparam RD_D3        =4'd3;
311
localparam RD_IDLE      =4'd5;
312 2 slai
 
313
reg [3:0] read_state;
314
reg [2:0] read_col;
315
reg              send_dq;
316
reg              send_dqs0;
317
reg              send_dqs1;
318
 
319
always@(posedge ck)
320
begin
321
        if(reset_n==1'b0)
322
                begin
323
                        read_state<=RD_IDLE;
324
                        read_col         <=0;
325
                        send_dq  <=0;
326
                end
327
        else
328
                begin
329
                        case(read_state)
330
                        RD_IDLE:begin
331
                        read_col<=0;
332
                        send_dq<=0;
333
                        if(read_cmd==OPCODE_READ)
334
                                begin
335
                                        read_state<=RD_D0;
336
                                end
337
                        else
338
                                begin
339
                                        read_state<=RD_IDLE;
340
                                end
341
                        end
342
                        RD_D0:begin
343
                                read_address12<=read_add[12];
344
                                read_state<=RD_D1;
345
                                read_col<=read_col+1'b1;
346
                                send_dq  <=1'b1;
347
                                $display("%m: at time %t\tREAD BANK[%x]\tROW[%x]\tCOL[%x]\tRD D0",$time,read_add[34:32],read_add[31:16],read_add[15:0]);
348
                        end
349
                        RD_D1:begin
350
                                if(read_address12==1'b1)
351
                                        begin
352
                                                read_state<=RD_D2;
353
                                                read_col<=read_col+1'b1;
354
                                        end
355
                                else if (read_cmd==OPCODE_READ)
356
                                        begin
357
                                                read_state<=RD_D0;
358
                                                read_col<=0;
359
                                                send_dq  <=1'b1;
360
                                        end
361
                                else
362
                                        begin
363
                                                read_state<=RD_IDLE;
364
                                                //send_dq        <=1'b0;
365
                                        end
366
                                $display("%m: at time %t\tREAD BANK[%x]\tROW[%x]\tCOL[%x]\tRD D1",$time,read_add[34:32],read_add[31:16],read_add[15:0]);
367
                        end
368
                        RD_D2:begin
369
                                read_state<=RD_D3;
370
                                read_col<=read_col+1'b1;
371
                                send_dq  <=1'b1;
372
                                $display("%m: at time %t\tREAD BANK[%x]\tROW[%x]\tCOL[%x]\tRD D2",$time,read_add[34:32],read_add[31:16],read_add[15:0]);
373
                        end
374
                        RD_D3:begin
375
                                //write_col<=write_col+1'b1;    
376
                                if (read_cmd==OPCODE_READ)
377
                                        begin
378
                                                read_state<=RD_D0;
379
                                                read_col<=0;
380
                                                send_dq  <=1'b1;
381
                                        end
382
                                else
383
                                        begin
384
                                                read_state<=RD_IDLE;
385
                                                read_col<=0;
386
                                                //send_dq        <=1'b0;
387
                                        end
388
                                        $display("%m: at time %t\tREAD BANK[%x]\tROW[%x]\tCOL[%x]\tRD D3",$time,read_add[34:32],read_add[31:16],read_add[15:0]);
389
                        end
390
                        endcase
391
                end
392
 
393
end //end always
394
 
395
//dqs fsm
396
always @(posedge ck_n)
397
begin
398
if(reset_n==1'b0)
399
        begin
400
                send_dqs1<=0;
401
                send_dqs0<=0;
402
        end
403
else
404
        begin
405
                if(read_cmd==OPCODE_READ)
406
                        begin
407
                                send_dqs1<=1'b1;
408
                        end
409
                else
410
                        begin
411
                                send_dqs1<=1'b0;
412
                        end
413
        end
414
send_dqs0<=send_dqs1;
415
end//end always
416
 
417
//ram here
418
dport_ram  #(
419 4 slai
        .DATA_WIDTH(MEM_DQ_WIDTH), //data_hi,data_lo
420 2 slai
        .ADDR_WIDTH(36)
421
)dport_ram_hi(
422
        .clk                    (ck),
423
        .di                     (data_hi),
424
        .read_addr      (read_add+read_col),
425
        .write_addr (write_add+write_col),
426
        .we                     (mem_we & data_hi_dm),
427
        .do                     (read_data[15:8])
428
);
429
 
430
dport_ram  #(
431 4 slai
        .DATA_WIDTH(MEM_DQ_WIDTH), //data_hi,data_lo
432 2 slai
        .ADDR_WIDTH(36)
433
)dport_ram_lo(
434
        .clk                    (ck),
435
        .di                     (data_lo),
436
        .read_addr      (read_add+read_col),
437
        .write_addr (write_add+write_col),
438
        .we                     (mem_we & data_lo_dm),
439
        .do                     (read_data[7:0])
440
);
441
assign dqs  =((send_dqs0==1'b1) || (send_dq==1'b1))?ck:1'bz;
442
assign dqs_n=((send_dqs0==1'b1) || (send_dq==1'b1))?ck_n:1'bz;
443
assign dq   = (send_dq==1'b1)?dq_out:8'hZZ;
444
 
445
/* utility functions to display information
446
*/
447 4 slai
 
448 2 slai
initial begin
449
        $timeformat (-9, 1, " ns", 1);
450
      end
451
 
452
always @(posedge ck )
453
begin
454
        case({cs_n,ras_n,cas_n,we_n})
455
 
456
        OPCODE_PRECHARGE        :begin
457 4 slai
                                        $display("%m: at time %t PRECHARGE ",$time);
458
                                end
459 2 slai
 
460
        OPCODE_ACTIVATE         :begin
461 4 slai
                                        $display("%m: at time %t ACTIVATE - BANK[%x]\tROW[%x]",$time,ba,a);
462
                                end
463 2 slai
 
464 4 slai
        OPCODE_DES              :begin
465
                                        $display("%m: at time %t DES ",$time);
466
                                end
467
        OPCODE_MRS      :begin
468
                                                        $display("%m: at time %t MRS - MR[%d]",$time,ba[1:0]);
469
                                                        case(ba[1:0])
470
                                                                2'b00:begin //MR0
471
                                                                        case(a[1:0]) // burst length
472
                                                                                2'b00:$display("%m\tBL = BL8 \(Fixed\)");
473
                                                                                2'b01:$display("%m\tBL = BC4/BL8 OTF");
474
                                                                                2'b10:$display("%m\tBL = BC4 (Fixed)");
475
                                                                                2'b11:$display("%m\tBL = Reserved");
476
                                                                        endcase
477
 
478
                                                                        case({a[6:4],a[2]}) //CAS Latency
479
                                                                                4'b0000:$display("%m\tCL = Reserved");
480
                                                                                4'b0010:$display("%m\tCL = 5");
481
                                                                                4'b0100:$display("%m\tCL = 6");
482
                                                                                4'b0110:$display("%m\tCL = 7");
483
                                                                                4'b1000:$display("%m\tCL = 8");
484
                                                                                4'b1010:$display("%m\tCL = 9");
485
                                                                                4'b1100:$display("%m\tCL = 10");
486
                                                                                4'b1111:$display("%m\tCL = 11(Optional for DD3-1600)");
487
                                                                                4'b0001:$display("%m\tCL = 12");
488
                                                                                4'b0011:$display("%m\tCL = 13");
489
                                                                                4'b0101:$display("%m\tCL = 14");
490
                                                                                4'b0111:$display("%m\tCL = Reserved for 15");
491
                                                                                4'b1001:$display("%m\tCL = Reserved for 16");
492
                                                                                4'b1011:$display("%m\tCL = Reserved");
493
                                                                                4'b1101:$display("%m\tCL = Reserved");
494
                                                                                4'b1111:$display("%m\tCL = Reserved");
495
                                                                        endcase
496
 
497
                                                                        case(a[11:9]) //Write Recover
498
                                                                                3'b000:$display("%m\tWR = 16^2(256 cycles)");
499
                                                                                3'b001:$display("%m\tWR =  5^2( 25 cycles)");
500
                                                                                3'b010:$display("%m\tWR =  6^2( 36 cycles)");
501
                                                                                3'b011:$display("%m\tWR =  7^2( 49 cycles)");
502
                                                                                3'b100:$display("%m\tWR =  8^2( 64 cycles)");
503
                                                                                3'b101:$display("%m\tWR = 10^2(100 cycles)");
504
                                                                                3'b110:$display("%m\tWR = 12^2(144 cycles)");
505
                                                                                3'b111:$display("%m\tWR = 14^2(196 cycles)");
506
                                                                        endcase
507
                                                                end//end MR0
508
                                                                2'b01:begin //MR1
509 6 slai
                                                                        case(a[0]) //DLL Enable
510
                                                                                1'b0:$display("%m\tDLL = Enabled");
511
                                                                                1'b1:$display("%m\tDLL = Disabled");
512
                                                                        endcase
513
                                                                        case({a[5],a[1]}) //Output driver impedence
514
                                                                                2'b00:$display("%m\tOutput Driver = RQZ/6(RQZ=240 Ohm)");
515
                                                                                2'b01:$display("%m\tOutput Driver = RQZ/7(RQZ=240 Ohm)");
516
                                                                                2'b10:$display("%m\tOutput Driver = Reserved");
517
                                                                                2'b11:$display("%m\tOutput Driver = Reserved");
518
                                                                        endcase
519
                                                                        case({a[9],a[6],a[2]})
520
                                                                                3'b000:$display("%m\tRTT Nom = RTT Nom Disabled");
521
                                                                                3'b001:$display("%m\tRTT Nom = RZQ/4(RZQ=240 Ohm)");
522
                                                                                3'b010:$display("%m\tRTT Nom = RZQ/2(RZQ=240 Ohm)");
523
                                                                                3'b011:$display("%m\tRTT Nom = RZQ/6(RZQ=240 Ohm)");
524
                                                                                3'b100:$display("%m\tRTT Nom = RZQ/12(RZQ=240 Ohm)");
525
                                                                                3'b101:$display("%m\tRTT Nom = RZQ/8(RZQ=240 Ohm)");
526
                                                                                3'b110:$display("%m\tRTT Nom = Reserved");
527
                                                                                3'b111:$display("%m\tRTT Nom = Reserved");
528
                                                                        endcase
529
                                                                        case(a[4:3]) //Additive Latency
530
                                                                                2'b00:$display("%m\tAL = 0(Disabled)");
531
                                                                                2'b01:$display("%m\tAL = CL-1");
532
                                                                                2'b10:$display("%m\tAL = CL-2");
533
                                                                                2'b11:$display("%m\tAL = Reserved");
534
                                                                        endcase
535 4 slai
                                                                end//end MR1
536
                                                                2'b10:begin //MR2
537 6 slai
                                                                        case(a[5:3])
538
                                                                                3'b000:$display("%m\tCWL = 5");
539
                                                                                3'b001:$display("%m\tCWL = 6");
540
                                                                                3'b010:$display("%m\tCWL = 7");
541
                                                                                3'b011:$display("%m\tCWL = 8");
542
                                                                                3'b100:$display("%m\tCWL = 9");
543
                                                                                3'b101:$display("%m\tCWL = 10");
544
                                                                                3'b110:$display("%m\tCWL = 11");
545
                                                                                3'b111:$display("%m\tCWL = 12");
546
                                                                        endcase
547
                                                                        case(a[10:9])
548
                                                                        2'b00:$display("%m\tDynamic ODT Off");
549
                                                                        2'b00:$display("%m\tRTT WR = RZQ/4(RQZ=240 Ohm)");
550
                                                                        2'b00:$display("%m\tRTT WR = RZQ/2(RQZ=240 Ohm)");
551
                                                                        2'b00:$display("%m\tRTT WR = Reserved");
552
                                                                        endcase
553 4 slai
                                                                end//end MR2
554
                                                                2'b11:begin //MR3
555
                                                                end//end MR3
556
                                                        endcase //end which MRS
557
 
558
 
559
                                                end //end MRS
560 2 slai
        /*OPCODE_NOP            :begin
561 4 slai
                                        /$display("%m: at time %t WRITE ",$time);
562
                                end
563 2 slai
        */
564
        /*
565
        OPCODE_READ             :begin
566 4 slai
                                        $display("%m: at time %t READ - BANK[%x]\tROW[%x]\tCOL[%x]",$time,ba,last_row,a);
567
                                end
568 2 slai
        OPCODE_WRITE            :begin
569 4 slai
                                        $display("%m: at time %t WRITE - BANK[%x]\tROW[%x],\tCOL[%x]",$time,ba,last_row,a);
570
                                end
571 2 slai
        */
572 4 slai
        OPCODE_ZQC              :begin
573
                                        $display("%m: at time %t ZQC ",$time);
574
                                end
575 2 slai
        endcase
576
 
577
end // end always@(*)
578
/* end utility*/
579
 
580
endmodule

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