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[/] [ddr3_synthesizable_bfm/] [trunk/] [rtl/] [ddr3_sr4.v] - Blame information for rev 2

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1 2 slai
/*
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Multibits Shift Register
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2010-2011 sclai <laikos@yahoo.com>
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This library is free software; you can redistribute it and/or modify it
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 under the terms of the GNU Lesser General Public License as published by
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 the Free Software Foundation; either version 2.1 of the License,
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 or (at your option) any later version.
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 This library is distributed in the hope that it will be useful, but
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 WITHOUT ANY WARRANTY; without even the implied warranty of
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 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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 Lesser General Public License for more details.
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 You should have received a copy of the GNU Lesser General Public
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 License along with this library; if not, write to the Free Software
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 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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 USA
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*/
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module ddr3_sr4 #(
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parameter PIPE_LEN=7
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)(
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input wire        clk,
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input wire [3:0] shift_in,
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output wire[3:0] shift_out
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);
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//register to hold value
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reg [PIPE_LEN-1:0] d0;
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reg [PIPE_LEN-1:0] d1;
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reg [PIPE_LEN-1:0] d2;
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reg [PIPE_LEN-1:0] d3;
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always @(posedge clk)
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begin
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  d3  <={shift_in[ 3],d3[PIPE_LEN-1:1]};
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  d2  <={shift_in[ 2],d2[PIPE_LEN-1:1]};
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  d1  <={shift_in[ 1],d1[PIPE_LEN-1:1]};
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  d0  <={shift_in[ 0],d0[PIPE_LEN-1:1]};
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end
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assign shift_out={d3[0],d2[0],d1[0],d0[0]};
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endmodule
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