OpenCores
URL https://opencores.org/ocsvn/ddr3_synthesizable_bfm/ddr3_synthesizable_bfm/trunk

Subversion Repositories ddr3_synthesizable_bfm

[/] [ddr3_synthesizable_bfm/] [trunk/] [rtl/] [my_oddrx8.v] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 slai
/*
2
Single Data Rate to Double Data Rate Output Register
3
2010-2011 sclai <laikos@yahoo.com>
4
 
5
This library is free software; you can redistribute it and/or modify it
6
 under the terms of the GNU Lesser General Public License as published by
7
 the Free Software Foundation; either version 2.1 of the License,
8
 or (at your option) any later version.
9
 
10
 This library is distributed in the hope that it will be useful, but
11
 WITHOUT ANY WARRANTY; without even the implied warranty of
12
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13
 Lesser General Public License for more details.
14
 
15
 You should have received a copy of the GNU Lesser General Public
16
 License along with this library; if not, write to the Free Software
17
 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
18
 USA
19
*/
20
module my_oddrx8(
21
input wire                      clk,
22
input wire [7:0]         d0,
23
input wire [7:0]         d1,
24
output reg [7:0]  io
25
);
26
 
27
 
28
 
29
always@(*)
30
begin
31
        case(clk)
32
        1'b0:io<=d1;
33
        1'b1:io<=d0;
34
        endcase
35
end
36
 
37
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.