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jdoin |
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
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<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
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<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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jdoin |
<TD ALIGN=CENTER COLSPAN='4'><B>debounce_atlys_top Project Status</B></TD></TR>
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jdoin |
<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
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<TD>debounce_vhdl_bench.xise</TD>
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<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
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jdoin |
<TD> No Errors </TD>
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jdoin |
</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
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<TD>debounce_atlys_top</TD>
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<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
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jdoin |
<TD>Synthesized</TD>
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jdoin |
</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
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<TD>xc6slx45-2csg324</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
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jdoin |
<TD> </TD>
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jdoin |
</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.1</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
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jdoin |
<TD> </TD>
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jdoin |
</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
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<TD>Balanced</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
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<TD>
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jdoin |
All Signals Completely Routed</TD>
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jdoin |
</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
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<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
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jdoin |
<TD>
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jdoin |
<A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
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jdoin |
</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
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jdoin |
<TD> </TD>
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jdoin |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
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jdoin |
<TD>0 </TD>
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jdoin |
</TR>
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</TABLE>
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jdoin |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
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<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
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<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
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jdoin |
<TD ALIGN=RIGHT>42</TD>
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jdoin |
<TD ALIGN=RIGHT>54,576</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD>
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jdoin |
<TD ALIGN=RIGHT>42</TD>
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jdoin |
<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latch-thrus</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as AND/OR logics</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
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7 |
jdoin |
<TD ALIGN=RIGHT>37</TD>
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jdoin |
<TD ALIGN=RIGHT>27,288</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD>
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7 |
jdoin |
<TD ALIGN=RIGHT>36</TD>
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6 |
jdoin |
<TD ALIGN=RIGHT>27,288</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
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<TD ALIGN=RIGHT>18</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
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7 |
jdoin |
<TD ALIGN=RIGHT>11</TD>
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6 |
jdoin |
<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
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| 113 |
7 |
jdoin |
<TD ALIGN=RIGHT>7</TD>
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| 114 |
6 |
jdoin |
<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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| 117 |
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ROM</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Memory</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD ALIGN=RIGHT>6,408</TD>
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<TD ALIGN=RIGHT>0%</TD>
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| 128 |
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used exclusively as route-thrus</TD>
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7 |
jdoin |
<TD ALIGN=RIGHT>1</TD>
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6 |
jdoin |
<TD> </TD>
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<TD> </TD>
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| 134 |
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<TD COLSPAN='2'> </TD>
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| 135 |
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice register load</TD>
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7 |
jdoin |
<TD ALIGN=RIGHT>0</TD>
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| 138 |
6 |
jdoin |
<TD> </TD>
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| 139 |
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<TD> </TD>
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| 140 |
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<TD COLSPAN='2'> </TD>
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| 141 |
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</TR>
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| 142 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice carry load</TD>
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| 143 |
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<TD ALIGN=RIGHT>1</TD>
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| 144 |
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<TD> </TD>
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| 145 |
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<TD> </TD>
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| 146 |
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<TD COLSPAN='2'> </TD>
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| 147 |
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with other load</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
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7 |
jdoin |
<TD ALIGN=RIGHT>19</TD>
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6 |
jdoin |
<TD ALIGN=RIGHT>6,822</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD COLSPAN='2'> </TD>
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| 159 |
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</TR>
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| 160 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
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| 161 |
7 |
jdoin |
<TD ALIGN=RIGHT>56</TD>
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| 162 |
6 |
jdoin |
<TD> </TD>
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<TD> </TD>
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| 164 |
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<TD COLSPAN='2'> </TD>
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| 165 |
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</TR>
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| 166 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD>
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| 167 |
7 |
jdoin |
<TD ALIGN=RIGHT>20</TD>
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<TD ALIGN=RIGHT>56</TD>
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| 169 |
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<TD ALIGN=RIGHT>35%</TD>
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| 170 |
6 |
jdoin |
<TD COLSPAN='2'> </TD>
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| 171 |
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</TR>
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| 172 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD>
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| 173 |
7 |
jdoin |
<TD ALIGN=RIGHT>19</TD>
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| 174 |
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<TD ALIGN=RIGHT>56</TD>
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<TD ALIGN=RIGHT>33%</TD>
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| 176 |
6 |
jdoin |
<TD COLSPAN='2'> </TD>
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| 177 |
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</TR>
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| 178 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD>
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| 179 |
7 |
jdoin |
<TD ALIGN=RIGHT>17</TD>
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<TD ALIGN=RIGHT>56</TD>
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<TD ALIGN=RIGHT>30%</TD>
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| 182 |
6 |
jdoin |
<TD COLSPAN='2'> </TD>
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| 183 |
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD>
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<TD ALIGN=RIGHT>3</TD>
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<TD> </TD>
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| 187 |
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<TD> </TD>
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| 188 |
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<TD COLSPAN='2'> </TD>
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| 189 |
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD>
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| 191 |
7 |
jdoin |
<TD ALIGN=RIGHT>6</TD>
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| 192 |
6 |
jdoin |
<TD ALIGN=RIGHT>54,576</TD>
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<TD ALIGN=RIGHT>1%</TD>
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| 194 |
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<TD COLSPAN='2'> </TD>
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| 195 |
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</TR>
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| 196 |
10 |
jdoin |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
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7 |
jdoin |
<TD ALIGN=RIGHT>31</TD>
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| 198 |
6 |
jdoin |
<TD ALIGN=RIGHT>218</TD>
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| 199 |
7 |
jdoin |
<TD ALIGN=RIGHT>14%</TD>
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| 200 |
6 |
jdoin |
<TD COLSPAN='2'> </TD>
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| 201 |
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of LOCed IOBs</TD>
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| 203 |
7 |
jdoin |
<TD ALIGN=RIGHT>31</TD>
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| 204 |
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<TD ALIGN=RIGHT>31</TD>
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| 205 |
6 |
jdoin |
<TD ALIGN=RIGHT>100%</TD>
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| 206 |
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<TD COLSPAN='2'> </TD>
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| 207 |
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</TR>
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| 208 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
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| 209 |
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<TD ALIGN=RIGHT>0</TD>
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| 210 |
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<TD ALIGN=RIGHT>116</TD>
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| 211 |
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<TD ALIGN=RIGHT>0%</TD>
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| 212 |
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<TD COLSPAN='2'> </TD>
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| 213 |
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</TR>
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| 214 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
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| 215 |
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<TD ALIGN=RIGHT>0</TD>
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| 216 |
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<TD ALIGN=RIGHT>232</TD>
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| 217 |
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<TD ALIGN=RIGHT>0%</TD>
|
| 218 |
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<TD COLSPAN='2'> </TD>
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| 219 |
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</TR>
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| 220 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
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| 221 |
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<TD ALIGN=RIGHT>0</TD>
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| 222 |
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<TD ALIGN=RIGHT>32</TD>
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| 223 |
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<TD ALIGN=RIGHT>0%</TD>
|
| 224 |
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<TD COLSPAN='2'> </TD>
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| 225 |
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</TR>
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| 226 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
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| 227 |
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<TD ALIGN=RIGHT>0</TD>
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| 228 |
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<TD ALIGN=RIGHT>32</TD>
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| 229 |
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<TD ALIGN=RIGHT>0%</TD>
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| 230 |
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<TD COLSPAN='2'> </TD>
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| 231 |
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</TR>
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| 232 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
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| 233 |
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<TD ALIGN=RIGHT>1</TD>
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| 234 |
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<TD ALIGN=RIGHT>16</TD>
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| 235 |
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<TD ALIGN=RIGHT>6%</TD>
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| 236 |
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<TD COLSPAN='2'> </TD>
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| 237 |
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</TR>
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| 238 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGs</TD>
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| 239 |
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<TD ALIGN=RIGHT>1</TD>
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| 240 |
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<TD> </TD>
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| 241 |
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<TD> </TD>
|
| 242 |
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<TD COLSPAN='2'> </TD>
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| 243 |
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</TR>
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| 244 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGMUX</TD>
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| 245 |
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<TD ALIGN=RIGHT>0</TD>
|
| 246 |
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<TD> </TD>
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| 247 |
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<TD> </TD>
|
| 248 |
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<TD COLSPAN='2'> </TD>
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| 249 |
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</TR>
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| 250 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
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| 251 |
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<TD ALIGN=RIGHT>0</TD>
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| 252 |
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<TD ALIGN=RIGHT>8</TD>
|
| 253 |
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<TD ALIGN=RIGHT>0%</TD>
|
| 254 |
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<TD COLSPAN='2'> </TD>
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| 255 |
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</TR>
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| 256 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
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| 257 |
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<TD ALIGN=RIGHT>0</TD>
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| 258 |
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<TD ALIGN=RIGHT>376</TD>
|
| 259 |
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<TD ALIGN=RIGHT>0%</TD>
|
| 260 |
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<TD COLSPAN='2'> </TD>
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| 261 |
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</TR>
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| 262 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
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| 263 |
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<TD ALIGN=RIGHT>0</TD>
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| 264 |
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<TD ALIGN=RIGHT>376</TD>
|
| 265 |
|
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<TD ALIGN=RIGHT>0%</TD>
|
| 266 |
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<TD COLSPAN='2'> </TD>
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| 267 |
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</TR>
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| 268 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
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| 269 |
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<TD ALIGN=RIGHT>0</TD>
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| 270 |
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<TD ALIGN=RIGHT>376</TD>
|
| 271 |
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<TD ALIGN=RIGHT>0%</TD>
|
| 272 |
|
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<TD COLSPAN='2'> </TD>
|
| 273 |
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</TR>
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| 274 |
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
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| 275 |
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<TD ALIGN=RIGHT>0</TD>
|
| 276 |
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<TD ALIGN=RIGHT>4</TD>
|
| 277 |
|
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<TD ALIGN=RIGHT>0%</TD>
|
| 278 |
|
|
<TD COLSPAN='2'> </TD>
|
| 279 |
|
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</TR>
|
| 280 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
|
| 281 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
| 282 |
|
|
<TD ALIGN=RIGHT>256</TD>
|
| 283 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
| 284 |
|
|
<TD COLSPAN='2'> </TD>
|
| 285 |
|
|
</TR>
|
| 286 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
|
| 287 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
| 288 |
|
|
<TD ALIGN=RIGHT>8</TD>
|
| 289 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
| 290 |
|
|
<TD COLSPAN='2'> </TD>
|
| 291 |
|
|
</TR>
|
| 292 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
|
| 293 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
| 294 |
|
|
<TD ALIGN=RIGHT>4</TD>
|
| 295 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
| 296 |
|
|
<TD COLSPAN='2'> </TD>
|
| 297 |
|
|
</TR>
|
| 298 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
|
| 299 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
| 300 |
|
|
<TD ALIGN=RIGHT>58</TD>
|
| 301 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
| 302 |
|
|
<TD COLSPAN='2'> </TD>
|
| 303 |
|
|
</TR>
|
| 304 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
|
| 305 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
| 306 |
|
|
<TD ALIGN=RIGHT>1</TD>
|
| 307 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
| 308 |
|
|
<TD COLSPAN='2'> </TD>
|
| 309 |
|
|
</TR>
|
| 310 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
|
| 311 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
| 312 |
|
|
<TD ALIGN=RIGHT>2</TD>
|
| 313 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
| 314 |
|
|
<TD COLSPAN='2'> </TD>
|
| 315 |
|
|
</TR>
|
| 316 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
|
| 317 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
| 318 |
|
|
<TD ALIGN=RIGHT>2</TD>
|
| 319 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
| 320 |
|
|
<TD COLSPAN='2'> </TD>
|
| 321 |
|
|
</TR>
|
| 322 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
|
| 323 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
| 324 |
|
|
<TD ALIGN=RIGHT>4</TD>
|
| 325 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
| 326 |
|
|
<TD COLSPAN='2'> </TD>
|
| 327 |
|
|
</TR>
|
| 328 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
|
| 329 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
| 330 |
|
|
<TD ALIGN=RIGHT>1</TD>
|
| 331 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
| 332 |
|
|
<TD COLSPAN='2'> </TD>
|
| 333 |
|
|
</TR>
|
| 334 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
|
| 335 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
| 336 |
|
|
<TD ALIGN=RIGHT>1</TD>
|
| 337 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
| 338 |
|
|
<TD COLSPAN='2'> </TD>
|
| 339 |
|
|
</TR>
|
| 340 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
|
| 341 |
|
|
<TD ALIGN=RIGHT>0</TD>
|
| 342 |
|
|
<TD ALIGN=RIGHT>1</TD>
|
| 343 |
|
|
<TD ALIGN=RIGHT>0%</TD>
|
| 344 |
|
|
<TD COLSPAN='2'> </TD>
|
| 345 |
|
|
</TR>
|
| 346 |
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
|
| 347 |
7 |
jdoin |
<TD ALIGN=RIGHT>2.37</TD>
|
| 348 |
6 |
jdoin |
<TD> </TD>
|
| 349 |
|
|
<TD> </TD>
|
| 350 |
|
|
<TD COLSPAN='2'> </TD>
|
| 351 |
|
|
</TR>
|
| 352 |
|
|
</TABLE>
|
| 353 |
3 |
jdoin |
|
| 354 |
|
|
|
| 355 |
|
|
|
| 356 |
6 |
jdoin |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
| 357 |
|
|
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
|
| 358 |
|
|
<TR ALIGN=LEFT>
|
| 359 |
|
|
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
|
| 360 |
|
|
<TD>0 (Setup: 0, Hold: 0)</TD>
|
| 361 |
|
|
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
|
| 362 |
10 |
jdoin |
<TD COLSPAN='2'><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
|
| 363 |
6 |
jdoin |
</TR>
|
| 364 |
|
|
<TR ALIGN=LEFT>
|
| 365 |
|
|
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
|
| 366 |
9 |
jdoin |
All Signals Completely Routed</TD>
|
| 367 |
6 |
jdoin |
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
|
| 368 |
10 |
jdoin |
<TD COLSPAN='2'><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
|
| 369 |
6 |
jdoin |
</TR>
|
| 370 |
|
|
<TR ALIGN=LEFT>
|
| 371 |
|
|
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
|
| 372 |
|
|
<TD>
|
| 373 |
10 |
jdoin |
<A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
|
| 374 |
6 |
jdoin |
<TD BGCOLOR='#FFFF99'><B> </B></TD>
|
| 375 |
|
|
<TD COLSPAN='2'> </TD>
|
| 376 |
|
|
</TABLE>
|
| 377 |
3 |
jdoin |
|
| 378 |
|
|
|
| 379 |
|
|
|
| 380 |
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
| 381 |
|
|
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
| 382 |
|
|
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
| 383 |
|
|
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
| 384 |
10 |
jdoin |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>seg 15. ago 23:25:02 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
| 385 |
9 |
jdoin |
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
| 386 |
10 |
jdoin |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>seg 15. ago 23:25:36 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
| 387 |
|
|
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>seg 15. ago 23:25:47 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
| 388 |
3 |
jdoin |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
| 389 |
10 |
jdoin |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>seg 15. ago 23:25:54 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
| 390 |
9 |
jdoin |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
| 391 |
3 |
jdoin |
</TABLE>
|
| 392 |
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
| 393 |
|
|
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
|
| 394 |
|
|
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
|
| 395 |
10 |
jdoin |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>seg 19. set 14:56:36 2011</TD></TR>
|
| 396 |
|
|
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>qui 11. ago 21:31:43 2011</TD></TR>
|
| 397 |
3 |
jdoin |
</TABLE>
|
| 398 |
|
|
|
| 399 |
|
|
|
| 400 |
10 |
jdoin |
<br><center><b>Date Generated:</b> 09/19/2011 - 15:37:38</center>
|
| 401 |
3 |
jdoin |
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