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[/] [dma_ahb/] [trunk/] [src/] [dma_ahb64/] [dma_ahb64.v] - Blame information for rev 4

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1 4 eyalhoc
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
29 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:32:58 2011
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//--
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//-- Source file: dma.v
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//---------------------------------------------------------
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module dma_ahb64(clk,reset,scan_en,idle,INT,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,pready,WHADDR0,WHBURST0,WHSIZE0,WHTRANS0,WHWDATA0,WHREADY0,WHRESP0,RHADDR0,RHBURST0,RHSIZE0,RHTRANS0,RHRDATA0,RHREADY0,RHRESP0);
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`include "dma_ahb64_defines.v"
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   input                                clk;
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   input                 reset;
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   input                 scan_en;
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   output                 idle;
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   output [1-1:0]                INT;
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   input [31:1]             periph_tx_req;
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   output [31:1]             periph_tx_clr;
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   input [31:1]             periph_rx_req;
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   output [31:1]             periph_rx_clr;
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   input                                pclken;
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   input                                psel;
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   input                                penable;
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   input [12:0]                         paddr;
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   input                                pwrite;
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   input [31:0]                         pwdata;
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   output [31:0]                        prdata;
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   output                               pslverr;
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   output                               pready;
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   output [32-1:0]              WHADDR0;
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   output [2:0]                         WHBURST0;
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   output [1:0]                         WHSIZE0;
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   output [1:0]                         WHTRANS0;
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   output [64-1:0]              WHWDATA0;
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   input                                WHREADY0;
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   input                                WHRESP0;
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   output [32-1:0]              RHADDR0;
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   output [2:0]                         RHBURST0;
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   output [1:0]                         RHSIZE0;
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   output [1:0]                         RHTRANS0;
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   input [64-1:0]               RHRDATA0;
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   input                                RHREADY0;
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   input                                RHRESP0;
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   wire                 rd_port_num0;
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   wire                 wr_port_num0;
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   wire                 rd_port_num1;
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   wire                 wr_port_num1;
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   wire                 slv_rd_port_num0;
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   wire                 slv_wr_port_num0;
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   wire                 slv_rd_port_num1;
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   wire                 slv_wr_port_num1;
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   wire [32-1:0]                WHADDR0;
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   wire [2:0]                           WHBURST0;
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   wire [1:0]                           WHSIZE0;
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   wire [1:0]                           WHTRANS0;
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   wire [64-1:0]                WHWDATA0;
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   wire                                 WHREADY0;
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   wire                                 WHRESP0;
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   wire [32-1:0]                RHADDR0;
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   wire [2:0]                           RHBURST0;
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   wire [1:0]                           RHSIZE0;
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   wire [1:0]                           RHTRANS0;
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   wire [64-1:0]                RHRDATA0;
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   wire                                 RHREADY0;
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   wire                                 RHRESP0;
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   wire                                 WHLAST0;
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   wire                                 WHOLD0;
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   wire                                 RHLAST0;
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   wire                                 RHOLD0;
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   wire [32-1:0]           M0_WHADDR;
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   wire [2:0]                           M0_WHBURST;
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   wire [1:0]                           M0_WHSIZE;
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   wire [1:0]                           M0_WHTRANS;
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   wire [64-1:0]           M0_WHWDATA;
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   wire                                 M0_WHREADY;
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   wire                                 M0_WHRESP;
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   wire [32-1:0]           M0_RHADDR;
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   wire [2:0]                           M0_RHBURST;
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   wire [1:0]                           M0_RHSIZE;
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   wire [1:0]                           M0_RHTRANS;
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   wire [64-1:0]           M0_RHRDATA;
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   wire                                 M0_RHREADY;
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   wire                                 M0_RHRESP;
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   wire                                 M0_WHLAST;
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   wire                                 M0_WHOLD;
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   wire                                 M0_RHLAST;
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   wire                                 M0_RHOLD;
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   wire [24-1:0]           M1_WHADDR;
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   wire [2:0]                           M1_WHBURST;
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   wire [1:0]                           M1_WHSIZE;
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   wire [1:0]                           M1_WHTRANS;
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   wire [32-1:0]           M1_WHWDATA;
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   wire                                 M1_WHREADY;
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   wire                                 M1_WHRESP;
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   wire [24-1:0]           M1_RHADDR;
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   wire [2:0]                           M1_RHBURST;
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   wire [1:0]                           M1_RHSIZE;
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   wire [1:0]                           M1_RHTRANS;
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   wire [32-1:0]           M1_RHRDATA;
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   wire                                 M1_RHREADY;
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   wire                                 M1_RHRESP;
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   wire                                 M1_WHLAST;
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   wire                                 M1_WHOLD;
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   wire                                 M1_RHLAST;
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   wire                                 M1_RHOLD;
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   wire [31:1]                 periph_tx_req;
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   wire [31:1]                 periph_rx_req;
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   wire [31:1]                 periph_tx_clr;
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   wire [31:1]                 periph_rx_clr;
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   assign                               WHADDR0   = M0_WHADDR;
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   assign                               WHBURST0   = M0_WHBURST;
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   assign                               WHSIZE0   = M0_WHSIZE;
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   assign                               WHTRANS0   = M0_WHTRANS;
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   assign                               WHWDATA0   = M0_WHWDATA;
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   assign                               RHADDR0   = M0_RHADDR;
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   assign                               RHBURST0   = M0_RHBURST;
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   assign                               RHSIZE0   = M0_RHSIZE;
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   assign                               RHTRANS0   = M0_RHTRANS;
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   assign                               WHLAST0   = M0_WHLAST;
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   assign                               RHLAST0   = M0_RHLAST;
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   assign                               M0_WHREADY  = WHREADY0;
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   assign                               M0_WHRESP  = WHRESP0;
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   assign                               M0_RHRDATA  = RHRDATA0;
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   assign                               M0_RHREADY  = RHREADY0;
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   assign                               M0_RHRESP  = RHRESP0;
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   assign                               M0_WHOLD  = WHOLD0;
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   assign                               M0_RHOLD  = RHOLD0;
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   assign                 RHOLD0 = 1'b0;
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   assign                 WHOLD0 = 1'b0;
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   dma_ahb64_dual_core
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   dma_ahb64_dual_core (
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             .clk(clk),
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             .reset(reset),
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             .scan_en(scan_en),
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             .idle(idle),
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             .INT(INT),
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             .periph_tx_req(periph_tx_req),
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             .periph_tx_clr(periph_tx_clr),
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             .periph_rx_req(periph_rx_req),
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             .periph_rx_clr(periph_rx_clr),
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                     .pclken(pclken),
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                     .psel(psel),
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                     .penable(penable),
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                     .paddr(paddr),
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                     .pwrite(pwrite),
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                     .pwdata(pwdata),
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                     .prdata(prdata),
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                     .pslverr(pslverr),
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                     .pready(pready),
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             .rd_port_num0(rd_port_num0),
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             .wr_port_num0(wr_port_num0),
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             .rd_port_num1(rd_port_num1),
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             .wr_port_num1(wr_port_num1),
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                     .M0_WHADDR(M0_WHADDR),
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                     .M0_WHBURST(M0_WHBURST),
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                     .M0_WHSIZE(M0_WHSIZE),
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                     .M0_WHTRANS(M0_WHTRANS),
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                     .M0_WHWDATA(M0_WHWDATA),
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                     .M0_WHREADY(M0_WHREADY),
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                     .M0_WHRESP(M0_WHRESP),
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                     .M0_RHADDR(M0_RHADDR),
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                     .M0_RHBURST(M0_RHBURST),
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                     .M0_RHSIZE(M0_RHSIZE),
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                     .M0_RHTRANS(M0_RHTRANS),
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                     .M0_RHRDATA(M0_RHRDATA),
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                     .M0_RHREADY(M0_RHREADY),
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                     .M0_RHRESP(M0_RHRESP),
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                     .M0_WHLAST(M0_WHLAST),
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                     .M0_WHOLD(M0_WHOLD),
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                     .M0_RHLAST(M0_RHLAST),
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                     .M0_RHOLD(M0_RHOLD)
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             );
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endmodule
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