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[/] [dma_ahb/] [trunk/] [src/] [dma_ahb64/] [dma_ahb64_apb_mux.v] - Blame information for rev 4

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1 4 eyalhoc
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
29 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:32:59 2011
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//--
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//-- Source file: dma_apb_mux.v
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//---------------------------------------------------------
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module  dma_ahb64_apb_mux (clk,reset,pclken,psel,penable,pwrite,paddr,prdata,pslverr,pready,psel0,prdata0,pslverr0,psel1,prdata1,pslverr1,psel_reg,prdata_reg,pslverr_reg);
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   input                 clk;
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   input                 reset;
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   input                 pclken;
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   input                 psel;
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   input                 penable;
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   input          pwrite;
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   input [12:11]      paddr;
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   output [31:0]         prdata;
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   output          pslverr;
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   output          pready;
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   output          psel0;
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   input [31:0]      prdata0;
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   input           pslverr0;
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   output          psel1;
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   input [31:0]      prdata1;
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   input           pslverr1;
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   output          psel_reg;
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   input [31:0]      prdata_reg;
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   input           pslverr_reg;
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   wire [31:0]          prdata_pre;
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   wire          pslverr_pre;
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   reg              pready;
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   assign          psel0    = pclken & psel & (paddr[12:11] == 2'b00);
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   assign          psel1    = pclken & psel & (paddr[12:11] == 2'b01);
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   assign          psel_reg = pclken & psel & (paddr[12] == 1'b1);
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   assign          prdata_pre  = prdata0 | prdata1 | prdata_reg;
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   assign          pslverr_pre = pslverr0 | pslverr1 | pslverr_reg;
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   assign          prdata = prdata_pre;
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   assign          pslverr = pslverr_pre;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       pready <= #1 1'b0;
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     else if (pclken)
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       pready <= #1 psel & (~penable);
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endmodule
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