Subversion Repositories dma_ahb

/////////////////////////////////////////////////////////////////////

////                                                             ////

////  Author: Eyal Hochberg                                      ////

////          eyal@provartec.com                                 ////

////                                                             ////

////  Downloaded from: http://www.opencores.org                  ////

/////////////////////////////////////////////////////////////////////

////                                                             ////

//// Copyright (C) 2010 Provartec LTD                            ////

//// www.provartec.com                                           ////

//// info@provartec.com                                          ////

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//// This source file may be used and distributed without        ////

//// restriction provided that this copyright statement is not   ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer.////

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//// This source file is free software; you can redistribute it  ////

//// and/or modify it under the terms of the GNU Lesser General  ////

//// Public License as published by the Free Software Foundation.////

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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////

//// PURPOSE.  See the GNU Lesser General Public License for more////

//// details. http://www.gnu.org/licenses/lgpl.html              ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

//---------------------------------------------------------

//-- File generated by RobustVerilog parser

//-- Version: 1.0

//-- Invoked Fri Mar 25 23:33:00 2011

//--

//-- Source file: dma_core_ahbm_timeout.v

//---------------------------------------------------------

module dma_ahb64_core0_ahbm_timeout(clk,reset,HTRANS,HREADY,ahb_timeout);

   input               clk;

   input               reset;

   input [1:0]               HTRANS;

   input               HREADY;

   output               ahb_timeout;

   wire               HVALID;

   reg [`TIMEOUT_BITS-1:0]    counter;

   assign               HVALID      = HTRANS[1];

   assign               ahb_timeout = (counter == 'd0);

   always @(posedge clk or posedge reset)

     if (reset)

       counter <= #1 {`TIMEOUT_BITS{1'b1}};

     else if (HVALID & HREADY)

       counter <= #1 {`TIMEOUT_BITS{1'b1}};

     else if (HVALID)

       counter <= #1 counter - 1'b1;

endmodule