URL
https://opencores.org/ocsvn/dma_ahb/dma_ahb/trunk
//---------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- Version: 1.0
//-- Invoked Fri Mar 25 23:32:59 2011
//--
//-- Source file: dma_core_wdt.v
//---------------------------------------------------------
module dma_ahb64_core0_wdt(clk,reset,ch_active,rd_burst_start,rd_ch_num,wr_burst_start,wr_ch_num,wdt_timeout,wdt_ch_num);
input clk;
input reset;
input [7:0] ch_active;
input rd_burst_start;
input [2:0] rd_ch_num;
input wr_burst_start;
input [2:0] wr_ch_num;
output wdt_timeout;
output [2:0] wdt_ch_num;
reg [`WDT_BITS-1:0] counter;
reg [2:0] wdt_ch_num;
wire current_ch_active;
wire current_burst_start;
wire advance;
wire idle;
assign idle = ch_active == 8'd0;
assign current_ch_active = ch_active[wdt_ch_num];
assign current_burst_start =
(rd_burst_start & (rd_ch_num == wdt_ch_num)) |
(wr_burst_start & (wr_ch_num == wdt_ch_num));
assign advance = (!current_ch_active) | current_burst_start | wdt_timeout;
always @(posedge clk or posedge reset)
if (reset)
wdt_ch_num <= #1 3'd0;
else if (advance)
wdt_ch_num <= #1 wdt_ch_num + 1'b1;
assign wdt_timeout = (counter == 'd0);
always @(posedge clk or posedge reset)
if (reset)
counter <= #1 {`WDT_BITS{1'b1}};
else if (advance | idle)
counter <= #1 {`WDT_BITS{1'b1}};
else
counter <= #1 counter - 1'b1;
endmodule
