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[/] [dma_axi/] [trunk/] [src/] [dma_axi32/] [dma_axi32_core0_ch_calc_joint.v] - Blame information for rev 2

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//---------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- Version: 1.0
//-- Invoked Fri Mar 25 23:34:54 2011
//--
//-- Source file: dma_ch_calc_joint.v
//---------------------------------------------------------
 
 
 
module dma_axi32_core0_ch_calc_joint(clk,reset,joint_update,ch_end,ch_end_flush,joint_line_req_clr,wr_cmd_pending,burst_size_pre2,burst_max_size,fifo_not_ready,outs_empty,x_remain,fifo_wr_ready,fifo_remain,joint,page_cross,joint_cross,joint_ready_in,joint_ready_out,joint_line_req,joint_burst_req,joint_wait,joint_flush,joint_flush_in,joint_buffer_small);
 
 
   parameter               READ          = 0;
   parameter            WRITE         = !READ;
 
   input                   clk;
   input            reset;
 
   input            joint_update;
   input            ch_end;
   input            ch_end_flush;
 
   input            joint_line_req_clr;
   input            wr_cmd_pending;
   input [7-1:0]  burst_size_pre2;
   input [7-1:0]  burst_max_size;
   input            fifo_not_ready;
   input            outs_empty;
   input [10-1:0]   x_remain;
   input            fifo_wr_ready;
   input [5:0]        fifo_remain;
 
   input            joint;
   input            page_cross;
   input            joint_cross;
   input            joint_ready_in;
   output            joint_ready_out;
   output            joint_line_req;
   output            joint_burst_req;
   output            joint_wait;
   output            joint_flush;
   input            joint_flush_in;
   output            joint_buffer_small;
 
 
 
 
   parameter            IDLE        = 3'd0;
   parameter            REQ_LINE    = 3'd1;
   parameter            READY_OUT   = 3'd2;
   parameter            READY       = 3'd3;
   parameter            CROSS       = 3'd4;
   parameter            BURST_REQ   = 3'd5;
   parameter            RECHK       = 3'd6;
   parameter            FLUSH       = 3'd7;
 
 
 
   reg [2:0]            ps;
   reg [2:0]            ns;
 
   wire            joint_ready_out_pre;
   reg                joint_ready_out;
   reg                joint_line_req;
   reg                joint_burst_req;
   reg                joint_flush;
   reg                joint_wait;
   wire            joint_buffer_small;
 
 
 
 
   assign            joint_ready_out_pre = joint & (burst_size_pre2 == burst_max_size) & (|burst_max_size) &
                                                 (~joint_line_req) & (~joint_burst_req);
 
   assign            joint_buffer_small = (burst_max_size > x_remain) | (x_remain < 'd8);
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       joint_ready_out <= #1 1'b0;
     else if ((page_cross | ch_end_flush | joint_flush | joint_wait) & (~ch_end))
       joint_ready_out <= #1 1'b0;
     else if ((~ch_end) & (~wr_cmd_pending))
       joint_ready_out <= #1 joint_ready_out_pre;
 
 
   always @(/*AUTOSENSE*/ch_end_flush or fifo_not_ready or fifo_remain
        or fifo_wr_ready or joint_buffer_small or joint_cross
        or joint_flush_in or joint_line_req_clr or joint_ready_in
        or joint_ready_out or outs_empty or page_cross or ps)
     begin
    ns              = IDLE;
    joint_line_req  = 1'b0;
    joint_burst_req = 1'b0;
    joint_flush     = 1'b0;
    joint_wait      = 1'b0;
 
    case (ps)
 
      IDLE :
        begin
           if (joint_flush_in | joint_buffer_small)
         ns = FLUSH;
           else if (joint_ready_out & joint_ready_in & outs_empty)
         ns = READY;
           else if (joint_ready_out)
         begin
            joint_wait = 1'b1;
            ns = READY_OUT;
         end
           else if (fifo_not_ready & joint_ready_in & outs_empty)
         if (WRITE)
           begin
              joint_line_req = 1'b1; //from write to read - fill fifo at begining
              ns = REQ_LINE;
           end
         else
           begin
              joint_burst_req = 1'b1; //from read to write - empty fifo after cross
              ns = REQ_LINE; //1 cycle pulse
           end
           else
         ns = IDLE;
        end
 
      REQ_LINE :
        begin
           if (joint_flush_in)
         ns = FLUSH;
           else if (joint_line_req_clr)
         begin
            ns = IDLE;
            joint_wait = 1'b0;
         end
           else
         begin
            ns = REQ_LINE;
            joint_wait = 1'b1;
         end
        end
 
      READY_OUT :
        begin
           joint_wait = 1'b1;
 
           if (joint_cross | page_cross)
         ns = CROSS;
           else if ((~joint_ready_out) | joint_flush_in | joint_buffer_small)
         ns = FLUSH;
           else if (joint_ready_in & outs_empty)
         begin
            joint_wait = 1'b0;
            ns = RECHK;
         end
           else
         ns = READY_OUT;
        end
 
      RECHK :
        begin
           if (joint_flush_in | joint_buffer_small)
         ns = FLUSH;
           else if (joint_ready_in & joint_ready_out)
         ns = READY;
           else if (WRITE)
         begin
            joint_line_req = 1'b1; //from write to read - read more data when AHB gets out of align address
            ns = REQ_LINE;
         end
           else if (READ)
         ns = RECHK;
        end
 
      READY :
        begin
           if (joint_cross)
         begin
            joint_wait = 1'b1;
            ns = READY_OUT;
         end
           else if ((~joint_ready_out) | (~joint_ready_in) | ch_end_flush)
           ns = FLUSH;
           else
         ns = READY;
        end
 
      CROSS :
        begin
           if (joint_buffer_small)
         ns = FLUSH;
           else if (joint_ready_out & (~joint_cross) & outs_empty)
         begin
            if (fifo_wr_ready & (fifo_remain <= 'd16)) //rd_gap
              begin
             joint_burst_req = 1'b1; //from read to write - empty fifo after cross
 
             if (fifo_remain == 'd0)
               ns = BURST_REQ; //2 cycles pulse
             else
               ns = REQ_LINE; //1 cycle pulse
              end
            else
              ns = IDLE;
         end
           else
         ns = CROSS;
        end
 
      BURST_REQ :
        begin
           joint_burst_req = 1'b1; //from read to write - empty fifo after cross
           ns = REQ_LINE;
        end
 
      FLUSH :
        begin
           joint_flush = 1'b1;
           ns = FLUSH;
        end
 
      default :
        ns = IDLE;
 
    endcase
     end
 
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       ps <= #1 IDLE;
     else if (joint_update)
       ps <= #1 IDLE;
     else
       ps <= #1 ns;
 
 
endmodule
 
 
 
 

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[/] [dma_axi/] [trunk/] [src/] [dma_axi32/] [dma_axi32_core0_ch_calc_joint.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	eyalhoc	`//---------------------------------------------------------`
2			`//-- File generated by RobustVerilog parser`
3			`//-- Version: 1.0`
4			`//-- Invoked Fri Mar 25 23:34:54 2011`
5			`//--`
6			`//-- Source file: dma_ch_calc_joint.v`
7			`//---------------------------------------------------------`
8
9
10
11			`module dma_axi32_core0_ch_calc_joint(clk,reset,joint_update,ch_end,ch_end_flush,joint_line_req_clr,wr_cmd_pending,burst_size_pre2,burst_max_size,fifo_not_ready,outs_empty,x_remain,fifo_wr_ready,fifo_remain,joint,page_cross,joint_cross,joint_ready_in,joint_ready_out,joint_line_req,joint_burst_req,joint_wait,joint_flush,joint_flush_in,joint_buffer_small);`
12
13
14			`parameter READ = 0;`
15			`parameter WRITE = !READ;`
16
17			`input clk;`
18			`input reset;`
19
20			`input joint_update;`
21			`input ch_end;`
22			`input ch_end_flush;`
23
24			`input joint_line_req_clr;`
25			`input wr_cmd_pending;`
26			`input [7-1:0] burst_size_pre2;`
27			`input [7-1:0] burst_max_size;`
28			`input fifo_not_ready;`
29			`input outs_empty;`
30			`input [10-1:0] x_remain;`
31			`input fifo_wr_ready;`
32			`input [5:0] fifo_remain;`
33
34			`input joint;`
35			`input page_cross;`
36			`input joint_cross;`
37			`input joint_ready_in;`
38			`output joint_ready_out;`
39			`output joint_line_req;`
40			`output joint_burst_req;`
41			`output joint_wait;`
42			`output joint_flush;`
43			`input joint_flush_in;`
44			`output joint_buffer_small;`
45
46
47
48
49			`parameter IDLE = 3'd0;`
50			`parameter REQ_LINE = 3'd1;`
51			`parameter READY_OUT = 3'd2;`
52			`parameter READY = 3'd3;`
53			`parameter CROSS = 3'd4;`
54			`parameter BURST_REQ = 3'd5;`
55			`parameter RECHK = 3'd6;`
56			`parameter FLUSH = 3'd7;`
57
58
59
60			`reg [2:0] ps;`
61			`reg [2:0] ns;`
62
63			`wire joint_ready_out_pre;`
64			`reg joint_ready_out;`
65			`reg joint_line_req;`
66			`reg joint_burst_req;`
67			`reg joint_flush;`
68			`reg joint_wait;`
69			`wire joint_buffer_small;`
70
71
72
73
74			`assign joint_ready_out_pre = joint & (burst_size_pre2 == burst_max_size) & (\|burst_max_size) &`
75			`(~joint_line_req) & (~joint_burst_req);`
76
77			`assign joint_buffer_small = (burst_max_size > x_remain) \| (x_remain < 'd8);`
78
79
80			`always @(posedge clk or posedge reset)`
81			`if (reset)`
82			`joint_ready_out <= #1 1'b0;`
83			`else if ((page_cross \| ch_end_flush \| joint_flush \| joint_wait) & (~ch_end))`
84			`joint_ready_out <= #1 1'b0;`
85			`else if ((~ch_end) & (~wr_cmd_pending))`
86			`joint_ready_out <= #1 joint_ready_out_pre;`
87
88
89			`always @(/AUTOSENSE/ch_end_flush or fifo_not_ready or fifo_remain`
90			`or fifo_wr_ready or joint_buffer_small or joint_cross`
91			`or joint_flush_in or joint_line_req_clr or joint_ready_in`
92			`or joint_ready_out or outs_empty or page_cross or ps)`
93			`begin`
94			`ns = IDLE;`
95			`joint_line_req = 1'b0;`
96			`joint_burst_req = 1'b0;`
97			`joint_flush = 1'b0;`
98			`joint_wait = 1'b0;`
99
100			`case (ps)`
101
102			`IDLE :`
103			`begin`
104			`if (joint_flush_in \| joint_buffer_small)`
105			`ns = FLUSH;`
106			`else if (joint_ready_out & joint_ready_in & outs_empty)`
107			`ns = READY;`
108			`else if (joint_ready_out)`
109			`begin`
110			`joint_wait = 1'b1;`
111			`ns = READY_OUT;`
112			`end`
113			`else if (fifo_not_ready & joint_ready_in & outs_empty)`
114			`if (WRITE)`
115			`begin`
116			`joint_line_req = 1'b1; //from write to read - fill fifo at begining`
117			`ns = REQ_LINE;`
118			`end`
119			`else`
120			`begin`
121			`joint_burst_req = 1'b1; //from read to write - empty fifo after cross`
122			`ns = REQ_LINE; //1 cycle pulse`
123			`end`
124			`else`
125			`ns = IDLE;`
126			`end`
127
128			`REQ_LINE :`
129			`begin`
130			`if (joint_flush_in)`
131			`ns = FLUSH;`
132			`else if (joint_line_req_clr)`
133			`begin`
134			`ns = IDLE;`
135			`joint_wait = 1'b0;`
136			`end`
137			`else`
138			`begin`
139			`ns = REQ_LINE;`
140			`joint_wait = 1'b1;`
141			`end`
142			`end`
143
144			`READY_OUT :`
145			`begin`
146			`joint_wait = 1'b1;`
147
148			`if (joint_cross \| page_cross)`
149			`ns = CROSS;`
150			`else if ((~joint_ready_out) \| joint_flush_in \| joint_buffer_small)`
151			`ns = FLUSH;`
152			`else if (joint_ready_in & outs_empty)`
153			`begin`
154			`joint_wait = 1'b0;`
155			`ns = RECHK;`
156			`end`
157			`else`
158			`ns = READY_OUT;`
159			`end`
160
161			`RECHK :`
162			`begin`
163			`if (joint_flush_in \| joint_buffer_small)`
164			`ns = FLUSH;`
165			`else if (joint_ready_in & joint_ready_out)`
166			`ns = READY;`
167			`else if (WRITE)`
168			`begin`
169			`joint_line_req = 1'b1; //from write to read - read more data when AHB gets out of align address`
170			`ns = REQ_LINE;`
171			`end`
172			`else if (READ)`
173			`ns = RECHK;`
174			`end`
175
176			`READY :`
177			`begin`
178			`if (joint_cross)`
179			`begin`
180			`joint_wait = 1'b1;`
181			`ns = READY_OUT;`
182			`end`
183			`else if ((~joint_ready_out) \| (~joint_ready_in) \| ch_end_flush)`
184			`ns = FLUSH;`
185			`else`
186			`ns = READY;`
187			`end`
188
189			`CROSS :`
190			`begin`
191			`if (joint_buffer_small)`
192			`ns = FLUSH;`
193			`else if (joint_ready_out & (~joint_cross) & outs_empty)`
194			`begin`
195			`if (fifo_wr_ready & (fifo_remain <= 'd16)) //rd_gap`
196			`begin`
197			`joint_burst_req = 1'b1; //from read to write - empty fifo after cross`
198
199			`if (fifo_remain == 'd0)`
200			`ns = BURST_REQ; //2 cycles pulse`
201			`else`
202			`ns = REQ_LINE; //1 cycle pulse`
203			`end`
204			`else`
205			`ns = IDLE;`
206			`end`
207			`else`
208			`ns = CROSS;`
209			`end`
210
211			`BURST_REQ :`
212			`begin`
213			`joint_burst_req = 1'b1; //from read to write - empty fifo after cross`
214			`ns = REQ_LINE;`
215			`end`
216
217			`FLUSH :`
218			`begin`
219			`joint_flush = 1'b1;`
220			`ns = FLUSH;`
221			`end`
222
223			`default :`
224			`ns = IDLE;`
225
226			`endcase`
227			`end`
228
229
230
231			`always @(posedge clk or posedge reset)`
232			`if (reset)`
233			`ps <= #1 IDLE;`
234			`else if (joint_update)`
235			`ps <= #1 IDLE;`
236			`else`
237			`ps <= #1 ns;`
238
239
240			`endmodule`
241
242
243
244