OpenCores
URL https://opencores.org/ocsvn/dma_axi/dma_axi/trunk

Subversion Repositories dma_axi

[/] [dma_axi/] [trunk/] [src/] [dma_axi32/] [dma_axi32_core0_ch_empty.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 eyalhoc 
//---------------------------------------------------------
2 
//-- File generated by RobustVerilog parser
3 
//-- Version: 1.0
4 
//-- Invoked Fri Mar 25 23:34:54 2011
5 
//--
6 
//-- Source file: dma_ch.v
7 
//---------------------------------------------------------
8 
 
9 
 
10 
 
11 
 
12 
module dma_axi32_core0_ch_empty (clk,reset,scan_en,pclk,clken,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,rd_cmd_split,rd_cmd_line,rd_clr_line,rd_clr,rd_clr_load,rd_slverr,rd_decerr,wr_cmd_split,wr_cmd_pending,wr_clr_line,wr_clr,wr_clr_last,wr_slverr,wr_decerr,load_wr,load_wr_cycle,load_wdata,load_req_in_prog,int_all_proc,ch_start,idle,ch_active,ch_rd_active,ch_wr_active,wr_last_cmd,rd_line_cmd,wr_line_cmd,rd_go_next_line,wr_go_next_line,rd_ready,rd_burst_start,rd_burst_addr,rd_burst_size,rd_tokens,rd_port_num,rd_periph_delay,rd_clr_valid,rd_transfer,rd_transfer_size,rd_clr_stall,wr_ready,wr_burst_start,wr_burst_addr,wr_burst_size,wr_tokens,wr_port_num,wr_periph_delay,wr_clr_valid,wr_transfer,wr_transfer_size,wr_next_size,wr_clr_stall,wr_incr,timeout_aw,timeout_w,timeout_ar,wdt_timeout,fifo_wr,fifo_wdata,fifo_wsize,fifo_rd,fifo_rsize,fifo_rd_valid,fifo_rdata,fifo_wr_ready,joint_mode,joint_remote,rd_page_cross,wr_page_cross,joint_in_prog,joint_not_in_prog,joint_mux_in_prog,joint_req);
13 
 
14 
   input             clk;
15 
   input             reset;
16 
   input             scan_en;
17 
 
18 
   input             pclk;
19 
   input             clken;
20 
   input             pclken;
21 
   input             psel;
22 
   input             penable;
23 
   input [7:0]             paddr;
24 
   input             pwrite;
25 
   input [31:0]         pwdata;
26 
   output [31:0]         prdata;
27 
   output             pslverr;
28 
 
29 
   input [31:1]         periph_tx_req;
30 
   output [31:1]         periph_tx_clr;
31 
   input [31:1]         periph_rx_req;
32 
   output [31:1]         periph_rx_clr;
33 
 
34 
   input             rd_cmd_split;
35 
   input             rd_cmd_line;
36 
   input             rd_clr_line;
37 
   input             rd_clr;
38 
   input             rd_clr_load;
39 
   input             rd_slverr;
40 
   input             rd_decerr;
41 
 
42 
   input             wr_cmd_split;
43 
   input             wr_cmd_pending;
44 
   input             wr_clr_line;
45 
   input             wr_clr;
46 
   input             wr_clr_last;
47 
   input             wr_slverr;
48 
   input             wr_decerr;
49 
 
50 
   input             load_wr;
51 
   input [1:0]             load_wr_cycle;
52 
   input [32-1:0]    load_wdata;
53 
   output             load_req_in_prog;
54 
 
55 
   output [1-1:0]    int_all_proc;
56 
   input              ch_start;
57 
   output             idle;
58 
   output             ch_active;
59 
   output             ch_rd_active;
60 
   output             ch_wr_active;
61 
   output             wr_last_cmd;
62 
   output             rd_line_cmd;
63 
   output             wr_line_cmd;
64 
   output             rd_go_next_line;
65 
   output             wr_go_next_line;
66 
 
67 
   output             rd_ready;
68 
   input             rd_burst_start;
69 
   output [32-1:0]   rd_burst_addr;
70 
   output [7-1:0]  rd_burst_size;
71 
   output [`TOKEN_BITS-1:0] rd_tokens;
72 
   output             rd_port_num;
73 
   output [`DELAY_BITS-1:0] rd_periph_delay;
74 
   output             rd_clr_valid;
75 
   input             rd_transfer;
76 
   input [3-1:0]    rd_transfer_size;
77 
   output             rd_clr_stall;
78 
 
79 
   output             wr_ready;
80 
   input             wr_burst_start;
81 
   output [32-1:0]   wr_burst_addr;
82 
   output [7-1:0]  wr_burst_size;
83 
   output [`TOKEN_BITS-1:0] wr_tokens;
84 
   output             wr_port_num;
85 
   output [`DELAY_BITS-1:0] wr_periph_delay;
86 
   output             wr_clr_valid;
87 
   input             wr_transfer;
88 
   input [3-1:0]    wr_transfer_size;
89 
   input [3-1:0]    wr_next_size;
90 
   output             wr_clr_stall;
91 
   output             wr_incr;
92 
 
93 
   input              timeout_aw;
94 
   input              timeout_w;
95 
   input              timeout_ar;
96 
   input             wdt_timeout;
97 
 
98 
   input             fifo_wr;
99 
   input [32-1:0]    fifo_wdata;
100 
   input [3-1:0]    fifo_wsize;
101 
 
102 
   input             fifo_rd;
103 
   input [3-1:0]    fifo_rsize;
104 
 
105 
   output             fifo_rd_valid;
106 
   output [32-1:0]   fifo_rdata;
107 
   output             fifo_wr_ready;
108 
 
109 
   input             joint_mode;
110 
   input             joint_remote;
111 
   input             rd_page_cross;
112 
   input             wr_page_cross;
113 
   output             joint_in_prog;
114 
   output             joint_not_in_prog;
115 
   output             joint_mux_in_prog;
116 
   output             joint_req;
117 
 
118 
 
119 
   assign             prdata            = 'd0;
120 
   assign             pslverr           = 'd1; //return error
121 
   assign             periph_tx_clr     = 'd0;
122 
   assign             periph_rx_clr     = 'd0;
123 
   assign             load_req_in_prog  = 'd0;
124 
   assign             int_all_proc      = 'd0;
125 
   assign             idle              = 'd1;
126 
   assign             ch_active         = 'd0;
127 
   assign             ch_rd_active      = 'd0;
128 
   assign             ch_wr_active      = 'd0;
129 
   assign             wr_last_cmd       = 'd0;
130 
   assign             rd_line_cmd       = 'd0;
131 
   assign             wr_line_cmd       = 'd0;
132 
   assign             rd_go_next_line   = 'd0;
133 
   assign             wr_go_next_line   = 'd0;
134 
   assign             rd_ready          = 'd0;
135 
   assign             rd_burst_addr     = 'd0;
136 
   assign             rd_burst_size     = 'd0;
137 
   assign             rd_tokens         = 'd0;
138 
   assign             rd_port_num       = 'd0;
139 
   assign             rd_periph_delay   = 'd0;
140 
   assign             rd_clr_valid      = 'd0;
141 
   assign             rd_clr_stall      = 'd0;
142 
   assign             wr_ready          = 'd0;
143 
   assign             wr_burst_addr     = 'd0;
144 
   assign             wr_burst_size     = 'd0;
145 
   assign             wr_tokens         = 'd0;
146 
   assign             wr_port_num       = 'd0;
147 
   assign             wr_periph_delay   = 'd0;
148 
   assign             wr_clr_valid      = 'd0;
149 
   assign             wr_clr_stall      = 'd0;
150 
   assign             wr_incr           = 'd0;
151 
   assign             fifo_rd_valid     = 'd0;
152 
   assign             fifo_rdata        = 'd0;
153 
   assign             fifo_wr_ready     = 'd0;
154 
   assign             joint_in_prog     = 'd0;
155 
   assign             joint_not_in_prog = 'd0;
156 
   assign             joint_mux_in_prog = 'd0;
157 
   assign             joint_req         = 'd0;
158 
 
159 
 
160 
 
161 
endmodule
162 
 
163 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.