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[/] [dma_axi/] [trunk/] [src/] [dma_axi32/] [dma_axi32_core0_ch_fifo_ptr.v] - Blame information for rev 2

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1 2 eyalhoc 
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:54 2011
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//--
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//-- Source file: dma_ch_fifo_ptr.v
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//---------------------------------------------------------
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module dma_axi32_core0_ch_fifo_ptr(clk,reset,joint_in_prog,wr_outstanding,ch_update,fifo_rd,fifo_rsize,slice_wr,slice_wr_fifo,slice_wsize,slice_rd,slice_rsize,rd_clr_line,wr_clr_line,wr_next_size,wr_burst_size,rd_ptr,wr_ptr,rd_line_remain,joint_delay,fifo_wr_ready,fifo_overflow,fifo_underflow);
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   input               clk;
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   input               reset;
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   input               joint_in_prog;
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   input               wr_outstanding;
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   input               ch_update;
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   input               fifo_rd;
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   input [3-1:0]      fifo_rsize;
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   input               slice_wr;
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   input               slice_wr_fifo;
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   input [3-1:0]      slice_wsize;
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   input               slice_rd;
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   input [3-1:0]      slice_rsize;
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   input               rd_clr_line;
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   input               wr_clr_line;
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   input [3-1:0]      wr_next_size;
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   input [7-1:0]     wr_burst_size;
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   output [5-1:0]     rd_ptr;
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   output [5-1:0]     wr_ptr;
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   output [3-1:0]     rd_line_remain;
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   output               joint_delay;
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   output               fifo_wr_ready;
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   output               fifo_overflow;
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   output               fifo_underflow;
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   wire [5-1:0]       rd_ptr_pre;
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   wire [5-1:0]       wr_ptr_pre;
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   reg [5-1:0]           rd_ptr;
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   reg [5-1:0]           wr_ptr;
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   wire [5+1:0]       fullness_pre; //signed
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   reg [5+1:0]           fullness; //signed
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   reg [3-1:0]           rd_line_remain;
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   wire               joint_in_prog_d;
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   reg                   joint_delay_reg;
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   reg                   fifo_wr_ready;
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   wire               fifo_overflow_pre;
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   wire               fifo_underflow_pre;
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   reg                   fifo_overflow;
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   reg                   fifo_underflow;
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   assign               wr_ptr_pre    = wr_ptr + ({3{slice_wr}} & slice_wsize);
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   assign               rd_ptr_pre    = rd_ptr + ({3{slice_rd}} & slice_rsize);
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   always @(posedge clk or posedge reset)
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     if (reset)
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       wr_ptr <= #1 {5{1'b0}};
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     else if (ch_update)
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       wr_ptr <= #1 {5{1'b0}};
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     else if (slice_wr)
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       wr_ptr <= #1 wr_ptr_pre;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       rd_ptr <= #1 {5{1'b0}};
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     else if (ch_update)
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       rd_ptr <= #1 {5{1'b0}};
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     else if (slice_rd)
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       rd_ptr <= #1 rd_ptr_pre;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       rd_line_remain <= #1 3'd4;
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     else if (ch_update | wr_clr_line)
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       rd_line_remain <= #1 3'd4;
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     else if (slice_rd & (rd_line_remain == slice_rsize))
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       rd_line_remain <= #1 3'd4;
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     else if (slice_rd)
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       rd_line_remain <= #1 rd_line_remain - slice_rsize;
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   assign               fullness_pre = fullness +
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                  ({3{slice_wr}} & slice_wsize) -
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                ({3{fifo_rd}} & fifo_rsize);
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   always @(posedge clk or posedge reset)
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     if (reset)
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       fullness <= #1 {5+2{1'b0}};
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     else if (ch_update)
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       fullness <= #1 {5+2{1'b0}};
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     else if (fifo_rd | slice_wr)
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       fullness <= #1 fullness_pre;
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   prgen_delay #(1) delay_joint_in_prog (.clk(clk), .reset(reset), .din(joint_in_prog), .dout(joint_in_prog_d));
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   always @(posedge clk or posedge reset)
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     if (reset)
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       joint_delay_reg <= #1 1'b0;
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     else if (joint_in_prog & (~joint_in_prog_d))
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       joint_delay_reg <= #1 fullness > 32 - 3'd4;
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     else if (~joint_in_prog)
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       joint_delay_reg <= #1 1'b0;
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   assign               joint_delay = joint_delay_reg;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       fifo_wr_ready <= #1 1'b0;
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     else if (joint_in_prog)
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       fifo_wr_ready <= #1 1'b0;
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     else if (|wr_next_size)
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       fifo_wr_ready <= #1 fullness_pre >= wr_next_size;
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   assign               fifo_underflow_pre =
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                              fullness[5+1];
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   assign               fifo_overflow_pre  = (~fullness[5+1]) & (fullness[5:0] > 32);
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   always @(posedge clk or posedge reset)
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     if (reset)
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       begin
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      fifo_overflow  <= #1 1'b0;
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      fifo_underflow <= #1 1'b0;
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       end
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     else if (ch_update)
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       begin
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      fifo_overflow  <= #1 1'b0;
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      fifo_underflow <= #1 1'b0;
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       end
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     else if ((!fifo_overflow) & (!fifo_underflow))
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       begin
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      fifo_overflow  <= #1 fifo_overflow_pre;
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      fifo_underflow <= #1 fifo_underflow_pre;
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       end
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endmodule
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