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//---------------------------------------------------------

//-- File generated by RobustVerilog parser

//-- Version: 1.0

//-- Invoked Fri Mar 25 23:34:54 2011

//--

//-- Source file: dma_ch_periph_mux.v

//---------------------------------------------------------

module dma_axi32_core0_ch_periph_mux(clk,reset,clken,periph_req,periph_clr,periph_ready,periph_num,clr_valid,clr);

   input                    clk;

   input             reset;

   input             clken;

   input [31:1]         periph_req;

   output [31:1]         periph_clr;

   output             periph_ready;

   input [4:0]              periph_num;

   input             clr_valid;

   input             clr;

   reg [31:1]             periph_clr;

   wire [31:0]             periph_req_full;

   wire             periph_ready_pre;

   always @(/*AUTOSENSE*/clken or clr or clr_valid or periph_num)

     begin

    periph_clr = {31{1'b0}};

    periph_clr[periph_num] = clr & clr_valid & clken;

     end

   assign periph_req_full  = {periph_req, 1'b1}; //bit 0 is memory

   assign periph_ready_pre = periph_req_full[periph_num];

   prgen_delay #(1) delay_ready  (.clk(clk), .reset(reset), .din(periph_ready_pre), .dout(periph_ready));

endmodule