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eyalhoc |
/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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eyalhoc |
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:53 2011
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//--
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//-- Source file: dma_ch_reg_size.v
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//---------------------------------------------------------
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module dma_axi32_core0_ch_reg_size(clk,reset,update,start_addr,burst_max_size_reg,burst_max_size_other,allow_full_burst,allow_full_fifo,joint_flush,burst_max_size);
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parameter MAX_BURST = 1 ? 64 : 128; //16 strobes
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parameter HALF_BYTES = 32/2;
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parameter LARGE_FIFO = 32 > MAX_BURST;
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parameter SMALL_FIFO = 32 == 16;
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input clk;
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input reset;
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input update;
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input [32-1:0] start_addr;
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input [7-1:0] burst_max_size_reg;
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input [7-1:0] burst_max_size_other;
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input allow_full_burst;
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input allow_full_fifo;
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input joint_flush;
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output [7-1:0] burst_max_size;
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wire [7-1:0] burst_max_size_fifo;
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wire [7-1:0] burst_max_size_pre;
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reg [7-1:0] burst_max_size;
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assign burst_max_size_fifo =
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allow_full_burst | LARGE_FIFO ? MAX_BURST :
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joint_flush & SMALL_FIFO ? HALF_BYTES :
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(burst_max_size_other > HALF_BYTES) & (burst_max_size_reg > HALF_BYTES) & (burst_max_size_other != burst_max_size_reg)
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? HALF_BYTES :
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allow_full_fifo ? 32 : HALF_BYTES;
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prgen_min2 #(7) min2_max(
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.a(burst_max_size_reg),
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.b(burst_max_size_fifo),
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.min(burst_max_size_pre)
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);
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always @(posedge clk or posedge reset)
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if (reset)
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burst_max_size <= #1 {7{1'b0}};
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else if (update)
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burst_max_size <= #1 burst_max_size_pre > MAX_BURST ? MAX_BURST : burst_max_size_pre;
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endmodule
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