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[/] [dma_axi/] [trunk/] [src/] [dma_axi32/] [dma_axi32_core0_ctrl.v] - Blame information for rev 2

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//---------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- Version: 1.0
//-- Invoked Fri Mar 25 23:34:51 2011
//--
//-- Source file: dma_core_ctrl.v
//---------------------------------------------------------
 
 
 
module dma_axi32_core0_ctrl(clk,reset,ch_go,cmd_full,cmd_pending,joint_req,ch_num,ch_num_resp,go_next_line,periph_clr_valid,periph_clr,periph_clr_last,periph_delay,clr_stall,tokens,ch_ready,ch_last,burst_start,finish,busy,hold);
 
 
   input                    clk;
   input             reset;
 
   input             ch_go;
 
   input             cmd_full;
   input             cmd_pending;
   input             joint_req;
 
   input [2:0]             ch_num;
   input [2:0]             ch_num_resp;
   input             go_next_line;
   input             periph_clr_valid;
   input             periph_clr;
   input             periph_clr_last;
   input [`DELAY_BITS-1:0]  periph_delay;
 
   input             clr_stall;
   input [`TOKEN_BITS-1:0]  tokens;
 
   input             ch_ready;
   input             ch_last;
   output             burst_start;
   output             finish;
   output             busy;
   input             hold;
 
 
   reg                 burst_start;
   reg                 finish;
   wire             tokens_remain;
   reg                 tokens_remain_reg;
   reg [`TOKEN_BITS-1:0]    tokens_counter;
   wire             stall;
   reg                 joint_ctrl_reg;
   wire             joint_ctrl;
 
   reg [`DELAY_BITS-1:0]    delay_counter;
 
   wire             periph_clr_ch;
   wire             periph_clr_last_ch;
   wire             go_next_line_d;
 
 
 
   reg [2:0]             ps;
   reg [2:0]             ns;
 
 
 
   parameter                IDLE        = 3'd0;
   parameter             CMD         = 3'd1;
   parameter             WAIT_CLR    = 3'd2;
   parameter             WAIT_DELAY  = 3'd3;
   parameter             STALL       = 3'd4;
 
 
   assign             busy = ps != IDLE;
 
   assign             periph_clr_ch      = periph_clr_valid & periph_clr & (ch_num == ch_num_resp);
   assign             periph_clr_last_ch = periph_clr_valid & periph_clr_last & (ch_num == ch_num_resp);
 
   assign             go_next_line_d = 1'b0;
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       joint_ctrl_reg <= #1 1'b0;
     else if (finish)
       joint_ctrl_reg <= #1 1'b0;
     else if (ch_go)
       joint_ctrl_reg <= #1 joint_req;
 
   assign             joint_ctrl = joint_ctrl_reg;
 
 
 
   assign             tokens_remain = (|tokens_counter) | ch_last;
 
   always @(posedge clk or posedge reset)
     if (reset)
       tokens_counter <= #1 {`TOKEN_BITS{1'b0}};
     else if (ch_go)
       tokens_counter <= #1 tokens;
     else if (burst_start & (|tokens_counter))
       tokens_counter <= #1 tokens_counter - 1'b1;
 
   always @(posedge clk or posedge reset)
     if (reset)
       delay_counter <= #1 {`DELAY_BITS{1'b0}};
     else if (periph_clr_ch)
       delay_counter <= #1 periph_delay;
     else if (|delay_counter)
       delay_counter <= #1 delay_counter - 1'b1;
 
 
   assign             stall  = cmd_pending | cmd_full | go_next_line_d;
 
 
   always @(/*AUTOSENSE*/ch_go or ch_last or ch_ready or clr_stall
        or delay_counter or go_next_line_d or hold or joint_ctrl
        or joint_req or periph_clr_ch or periph_clr_last_ch
        or periph_clr_valid or periph_delay or ps or stall
        or tokens_remain)
     begin
    ns          = IDLE;
    burst_start = 1'b0;
    finish  = 1'b0;
 
    case (ps)
      IDLE :
        begin
           if (ch_go)
         begin
            if (!ch_ready)
              begin
             ns = IDLE;
             finish = 1'b1;
              end
            else if (stall)
              ns = STALL;
            else
              ns = CMD;
         end
           else
         ns = IDLE;
        end
 
      CMD :
        begin
           if (joint_req ^ joint_ctrl) //change in joint_req
         begin
            ns = IDLE;
            finish = 1'b1;
         end
           else if ((clr_stall | hold) & tokens_remain)
         ns = CMD;
           else if (ch_ready & tokens_remain)
         begin
                    if (stall)
                      ns = STALL;
                    else
                      begin
                         burst_start = 1'b1;
                         ns = WAIT_CLR;
                      end
         end
           else if (ch_last & (~ch_ready))
         ns = CMD;
           else
         begin
            ns = IDLE;
            finish = 1'b1;
         end
        end
 
      WAIT_CLR :
        begin
           if ((|periph_delay) & periph_clr_valid) //don't wait for clr if not valid (block clr)
         begin
            if (periph_clr_last_ch) //release if load cmd
              begin
             ns = IDLE;
             finish = 1'b1;
              end
            else if (periph_clr_ch)
              ns = WAIT_DELAY;
            else
              ns = WAIT_CLR;
         end
           //memory - allow command depth
           else if (!tokens_remain)
         begin
            ns = IDLE;
            finish = 1'b1;
         end
           else
         ns = WAIT_DELAY;
        end
 
      WAIT_DELAY :
        begin
           if (go_next_line_d) //delay in case of cmd split (cross page)
         ns = WAIT_DELAY;
           else if (delay_counter == 'd0)
         ns = STALL;
           else
         ns = WAIT_DELAY;
        end
 
      STALL :
        begin
           if (ch_ready & tokens_remain)
         begin
            if (stall)
              ns = STALL;
            else
              ns = CMD;
         end
           else if (ch_last & (~ch_ready))
         ns = CMD;
           else
         begin
            ns = IDLE;
            finish = 1'b1;
         end
        end
 
      default :
        begin
           ns = IDLE;
        end
 
    endcase
     end
 
   always @(posedge clk or posedge reset)
     if (reset)
       ps <= #1 IDLE;
     else
       ps <= #1 ns;
 
 
endmodule
 
 
 
 
 

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[/] [dma_axi/] [trunk/] [src/] [dma_axi32/] [dma_axi32_core0_ctrl.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	eyalhoc	`//---------------------------------------------------------`
2			`//-- File generated by RobustVerilog parser`
3			`//-- Version: 1.0`
4			`//-- Invoked Fri Mar 25 23:34:51 2011`
5			`//--`
6			`//-- Source file: dma_core_ctrl.v`
7			`//---------------------------------------------------------`
8
9
10
11			`module dma_axi32_core0_ctrl(clk,reset,ch_go,cmd_full,cmd_pending,joint_req,ch_num,ch_num_resp,go_next_line,periph_clr_valid,periph_clr,periph_clr_last,periph_delay,clr_stall,tokens,ch_ready,ch_last,burst_start,finish,busy,hold);`
12
13
14			`input clk;`
15			`input reset;`
16
17			`input ch_go;`
18
19			`input cmd_full;`
20			`input cmd_pending;`
21			`input joint_req;`
22
23			`input [2:0] ch_num;`
24			`input [2:0] ch_num_resp;`
25			`input go_next_line;`
26			`input periph_clr_valid;`
27			`input periph_clr;`
28			`input periph_clr_last;`
29			input [`DELAY_BITS-1:0] periph_delay;
30
31			`input clr_stall;`
32			input [`TOKEN_BITS-1:0] tokens;
33
34			`input ch_ready;`
35			`input ch_last;`
36			`output burst_start;`
37			`output finish;`
38			`output busy;`
39			`input hold;`
40
41
42			`reg burst_start;`
43			`reg finish;`
44			`wire tokens_remain;`
45			`reg tokens_remain_reg;`
46			reg [`TOKEN_BITS-1:0] tokens_counter;
47			`wire stall;`
48			`reg joint_ctrl_reg;`
49			`wire joint_ctrl;`
50
51			reg [`DELAY_BITS-1:0] delay_counter;
52
53			`wire periph_clr_ch;`
54			`wire periph_clr_last_ch;`
55			`wire go_next_line_d;`
56
57
58
59			`reg [2:0] ps;`
60			`reg [2:0] ns;`
61
62
63
64			`parameter IDLE = 3'd0;`
65			`parameter CMD = 3'd1;`
66			`parameter WAIT_CLR = 3'd2;`
67			`parameter WAIT_DELAY = 3'd3;`
68			`parameter STALL = 3'd4;`
69
70
71			`assign busy = ps != IDLE;`
72
73			`assign periph_clr_ch = periph_clr_valid & periph_clr & (ch_num == ch_num_resp);`
74			`assign periph_clr_last_ch = periph_clr_valid & periph_clr_last & (ch_num == ch_num_resp);`
75
76			`assign go_next_line_d = 1'b0;`
77
78
79			`always @(posedge clk or posedge reset)`
80			`if (reset)`
81			`joint_ctrl_reg <= #1 1'b0;`
82			`else if (finish)`
83			`joint_ctrl_reg <= #1 1'b0;`
84			`else if (ch_go)`
85			`joint_ctrl_reg <= #1 joint_req;`
86
87			`assign joint_ctrl = joint_ctrl_reg;`
88
89
90
91			`assign tokens_remain = (\|tokens_counter) \| ch_last;`
92
93			`always @(posedge clk or posedge reset)`
94			`if (reset)`
95			tokens_counter <= #1 {`TOKEN_BITS{1'b0}};
96			`else if (ch_go)`
97			`tokens_counter <= #1 tokens;`
98			`else if (burst_start & (\|tokens_counter))`
99			`tokens_counter <= #1 tokens_counter - 1'b1;`
100
101			`always @(posedge clk or posedge reset)`
102			`if (reset)`
103			delay_counter <= #1 {`DELAY_BITS{1'b0}};
104			`else if (periph_clr_ch)`
105			`delay_counter <= #1 periph_delay;`
106			`else if (\|delay_counter)`
107			`delay_counter <= #1 delay_counter - 1'b1;`
108
109
110			`assign stall = cmd_pending \| cmd_full \| go_next_line_d;`
111
112
113			`always @(/AUTOSENSE/ch_go or ch_last or ch_ready or clr_stall`
114			`or delay_counter or go_next_line_d or hold or joint_ctrl`
115			`or joint_req or periph_clr_ch or periph_clr_last_ch`
116			`or periph_clr_valid or periph_delay or ps or stall`
117			`or tokens_remain)`
118			`begin`
119			`ns = IDLE;`
120			`burst_start = 1'b0;`
121			`finish = 1'b0;`
122
123			`case (ps)`
124			`IDLE :`
125			`begin`
126			`if (ch_go)`
127			`begin`
128			`if (!ch_ready)`
129			`begin`
130			`ns = IDLE;`
131			`finish = 1'b1;`
132			`end`
133			`else if (stall)`
134			`ns = STALL;`
135			`else`
136			`ns = CMD;`
137			`end`
138			`else`
139			`ns = IDLE;`
140			`end`
141
142			`CMD :`
143			`begin`
144			`if (joint_req ^ joint_ctrl) //change in joint_req`
145			`begin`
146			`ns = IDLE;`
147			`finish = 1'b1;`
148			`end`
149			`else if ((clr_stall \| hold) & tokens_remain)`
150			`ns = CMD;`
151			`else if (ch_ready & tokens_remain)`
152			`begin`
153			`if (stall)`
154			`ns = STALL;`
155			`else`
156			`begin`
157			`burst_start = 1'b1;`
158			`ns = WAIT_CLR;`
159			`end`
160			`end`
161			`else if (ch_last & (~ch_ready))`
162			`ns = CMD;`
163			`else`
164			`begin`
165			`ns = IDLE;`
166			`finish = 1'b1;`
167			`end`
168			`end`
169
170			`WAIT_CLR :`
171			`begin`
172			`if ((\|periph_delay) & periph_clr_valid) //don't wait for clr if not valid (block clr)`
173			`begin`
174			`if (periph_clr_last_ch) //release if load cmd`
175			`begin`
176			`ns = IDLE;`
177			`finish = 1'b1;`
178			`end`
179			`else if (periph_clr_ch)`
180			`ns = WAIT_DELAY;`
181			`else`
182			`ns = WAIT_CLR;`
183			`end`
184			`//memory - allow command depth`
185			`else if (!tokens_remain)`
186			`begin`
187			`ns = IDLE;`
188			`finish = 1'b1;`
189			`end`
190			`else`
191			`ns = WAIT_DELAY;`
192			`end`
193
194			`WAIT_DELAY :`
195			`begin`
196			`if (go_next_line_d) //delay in case of cmd split (cross page)`
197			`ns = WAIT_DELAY;`
198			`else if (delay_counter == 'd0)`
199			`ns = STALL;`
200			`else`
201			`ns = WAIT_DELAY;`
202			`end`
203
204			`STALL :`
205			`begin`
206			`if (ch_ready & tokens_remain)`
207			`begin`
208			`if (stall)`
209			`ns = STALL;`
210			`else`
211			`ns = CMD;`
212			`end`
213			`else if (ch_last & (~ch_ready))`
214			`ns = CMD;`
215			`else`
216			`begin`
217			`ns = IDLE;`
218			`finish = 1'b1;`
219			`end`
220			`end`
221
222			`default :`
223			`begin`
224			`ns = IDLE;`
225			`end`
226
227			`endcase`
228			`end`
229
230			`always @(posedge clk or posedge reset)`
231			`if (reset)`
232			`ps <= #1 IDLE;`
233			`else`
234			`ps <= #1 ns;`
235
236
237			`endmodule`
238
239
240
241
242