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[/] [dma_axi/] [trunk/] [src/] [dma_axi64/] [dma_axi64_core0_axim_cmd.v] - Blame information for rev 2

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//---------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- Version: 1.0
//-- Invoked Fri Mar 25 23:36:55 2011
//--
//-- Source file: dma_core_axim_cmd.v
//---------------------------------------------------------
 
 
 
module dma_axi64_core0_axim_cmd(clk,reset,ch_num,burst_start,burst_addr,burst_size,end_line_cmd,extra_bit,cmd_port,joint_req,joint_pending,cmd_pending,cmd_full,cmd_split,cmd_num,cmd_line,page_cross,AID,AADDR,APORT,ALEN,ASIZE,AVALID,AREADY,AWVALID,AJOINT,axim_timeout_num,axim_timeout);
 
   parameter                  AXI_WORD_SIZE = 0 ? 2'b10 : 2'b11;
   parameter                  AXI_3 = 0 ? 2 : 3;
 
   input               clk;
   input               reset;
 
   input [2:0]               ch_num;
 
   input               burst_start;
   input [32-1:0]      burst_addr;
   input [8-1:0]     burst_size;
   input               end_line_cmd;
   input               extra_bit;
   input               cmd_port;
   input               joint_req;
 
   output               joint_pending;
   output               cmd_pending;
   input               cmd_full;
   output               cmd_split;
   output [2:0]           cmd_num;
   output               cmd_line;
 
   output               page_cross;
 
   output [`CMD_BITS-1:0]     AID;
   output [32-1:0]     AADDR;
   output               APORT;
   output [`LEN_BITS-1:0]     ALEN;
   output [1:0]           ASIZE;
   output               AVALID;
   input               AREADY;
   input               AWVALID;
   output               AJOINT;
 
   output [2:0]           axim_timeout_num;
   output               axim_timeout;
 
 
 
   reg [`CMD_BITS-1:0]           AID;
   reg [`CMD_BITS-1:0]           AID_reg;
   reg [32-1:0]           AADDR;
   reg                   APORT;
   reg [`LEN_BITS-1:0]           ALEN;
   reg [1:0]               ASIZE;
   reg                   AVALID_reg;
   reg                   AJOINT;
 
 
   wire [`CMD_BITS-1:0]       AID_pre;
   wire [32-1:0]       AADDR_pre;
   wire [1:0]               ASIZE_pre;
   wire [`LEN_BITS-1:0]       ALEN_pre;
   wire [8-1:0]      burst_length;
 
   wire               cmd;
   reg                   cmd_pending;
   wire               cmd_line_pre;
   wire               cmd_line;
 
   wire               high_addr_pre;
   wire               high_addr;
   wire [8:0]               burst_reach_pre;
   reg [8:0]               burst_reach;
   reg                   joint_cross;
   wire               page_cross_pre;
   wire               page_cross;
   wire               cross_start;
   wire               cross_start_d;
   wire [8:0]               max_burst;
   reg [8:0]               max_burst_d;
   reg                   next_burst;
   reg [8-1:0]       next_burst_size;
   wire               next_burst_start;
 
 
 
 
   assign               high_addr_pre    = burst_addr[11:8] == 4'hf;
   assign               burst_reach_pre  = burst_addr[7:0] + burst_size;
   assign               page_cross       = high_addr & (burst_reach > {1'b1, {8{1'b0}}});
   assign               max_burst        = {1'b1, {8{1'b0}}} - burst_addr[7:0];
   assign               next_burst_start = next_burst & (~AVALID_reg) & (~cmd_full);
   assign               cross_start      = burst_start & page_cross;
 
 
   prgen_delay #(1) delay_high_addr (.clk(clk), .reset(reset), .din(high_addr_pre), .dout(high_addr));
   prgen_delay #(1) delay_cross_start (.clk(clk), .reset(reset), .din(cross_start), .dout(cross_start_d));
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       burst_reach <= #1 {9{1'b0}};
     else if (high_addr_pre)
       burst_reach <= #1 burst_reach_pre;
 
   always @(posedge clk or posedge reset)
     if (reset)
       next_burst <= #1 1'b0;
     else if (next_burst_start)
       next_burst <= #1 1'b0;
     else if (cross_start)
       next_burst <= #1 1'b1;
 
   always @(posedge clk or posedge reset)
     if (reset)
       max_burst_d <= #1 {9{1'b0}};
     else if (cross_start)
       max_burst_d <= #1 max_burst;
 
   always @(posedge clk or posedge reset)
     if (reset)
       next_burst_size <= #1 {8{1'b0}};
     else if (cross_start)
       next_burst_size <= #1 burst_size;
     else if (cross_start_d)
       next_burst_size <= #1 next_burst_size - max_burst_d;
 
   assign               cmd_split       = cross_start_d;
 
   assign               cmd             = AVALID & AREADY;
   assign               cmd_num         = AID[2:0];
   assign               cmd_line_pre    = cmd & AID[6];
 
   assign               joint_pending   = AVALID & (~AREADY) & AJOINT;
 
   always @(posedge clk or posedge reset)
     if (reset)
       cmd_pending <= #1 1'b0;
     else if (burst_start)
       cmd_pending <= #1 1'b1;
     else if (cmd & (~next_burst))
       cmd_pending <= #1 1'b0;
 
 
   prgen_delay #(1) delay_cmd_line (.clk(clk), .reset(reset), .din(cmd_line_pre), .dout(cmd_line));
 
   assign               AID_pre = {
                     end_line_cmd,   //[6]
                     ASIZE_pre[1:0], //[5:4]
                     extra_bit,      //[3]
                     ch_num[2:0]     //[2:0]
                     };
 
   assign               AADDR_pre = burst_addr;
 
   assign               ASIZE_pre =
                  burst_size == 'd1 ? 2'b00 :
                  burst_size == 'd2 ? 2'b01 :
                  burst_size == 'd4 ? 2'b10 :
                  AXI_WORD_SIZE;
 
   assign               burst_length =
                  next_burst    ? next_burst_size :
                  page_cross    ? max_burst       : burst_size;
 
   assign               ALEN_pre =
                  burst_length[8-1:AXI_3] == 'd0 ? {`LEN_BITS{1'b0}} :
                  burst_length[8-1:AXI_3] - 1'b1;
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       begin
      ASIZE  <= #1 {2{1'b0}};
      AJOINT <= #1 1'b0;
       end
     else if (burst_start)
       begin
      ASIZE  <= #1 ASIZE_pre;
      AJOINT <= #1 joint_req;
       end
 
   always @(posedge clk or posedge reset)
     if (reset)
       AID_reg <= #1 {`CMD_BITS{1'b0}};
     else if (burst_start)
       AID_reg <= #1 AID_pre;
 
   always @(AID_reg or next_burst)
     begin
    AID               = AID_reg;
    AID[`ID_END_LINE] = AID_reg[`ID_END_LINE] & (~next_burst);
    AID[`ID_LAST]     = AID_reg[`ID_LAST] & (~next_burst);
     end
 
   always @(posedge clk or posedge reset)
     if (reset)
       AADDR  <= #1 {32{1'b0}};
     else if (next_burst_start)
       AADDR  <= #1 {AADDR[32-1:12], {12{1'b1}}} + 1'b1;
     else if (burst_start)
       AADDR  <= #1 AADDR_pre;
 
   always @(posedge clk or posedge reset)
     if (reset)
       APORT <= #1 1'b0;
     else if (burst_start)
       APORT <= #1 cmd_port;
 
   always @(posedge clk or posedge reset)
     if (reset)
       ALEN   <= #1 {`LEN_BITS{1'b0}};
     else if (burst_start | next_burst_start)
       ALEN   <= #1 ALEN_pre;
 
   always @(posedge clk or posedge reset)
     if (reset)
       AVALID_reg <= #1 1'b0;
     else if (AVALID & AREADY)
       AVALID_reg <= #1 1'b0;
     else if ((burst_start & (burst_size > 'd0)) | next_burst_start)
       AVALID_reg <= #1 1'b1;
 
   assign AVALID = AJOINT ? AVALID_reg & (~AWVALID) : AVALID_reg;
 
   dma_axi64_core0_axim_timeout  dma_axi64_axim_timeout (
                         .clk(clk),
                         .reset(reset),
                         .VALID(AVALID),
                         .READY(AREADY),
                         .ID(AID),
                         .axim_timeout_num(axim_timeout_num),
                         .axim_timeout(axim_timeout)
                         );
 
 
endmodule
 
 
 
 
 

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[/] [dma_axi/] [trunk/] [src/] [dma_axi64/] [dma_axi64_core0_axim_cmd.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	eyalhoc	`//---------------------------------------------------------`
2			`//-- File generated by RobustVerilog parser`
3			`//-- Version: 1.0`
4			`//-- Invoked Fri Mar 25 23:36:55 2011`
5			`//--`
6			`//-- Source file: dma_core_axim_cmd.v`
7			`//---------------------------------------------------------`
8
9
10
11			`module dma_axi64_core0_axim_cmd(clk,reset,ch_num,burst_start,burst_addr,burst_size,end_line_cmd,extra_bit,cmd_port,joint_req,joint_pending,cmd_pending,cmd_full,cmd_split,cmd_num,cmd_line,page_cross,AID,AADDR,APORT,ALEN,ASIZE,AVALID,AREADY,AWVALID,AJOINT,axim_timeout_num,axim_timeout);`
12
13			`parameter AXI_WORD_SIZE = 0 ? 2'b10 : 2'b11;`
14			`parameter AXI_3 = 0 ? 2 : 3;`
15
16			`input clk;`
17			`input reset;`
18
19			`input [2:0] ch_num;`
20
21			`input burst_start;`
22			`input [32-1:0] burst_addr;`
23			`input [8-1:0] burst_size;`
24			`input end_line_cmd;`
25			`input extra_bit;`
26			`input cmd_port;`
27			`input joint_req;`
28
29			`output joint_pending;`
30			`output cmd_pending;`
31			`input cmd_full;`
32			`output cmd_split;`
33			`output [2:0] cmd_num;`
34			`output cmd_line;`
35
36			`output page_cross;`
37
38			output [`CMD_BITS-1:0] AID;
39			`output [32-1:0] AADDR;`
40			`output APORT;`
41			output [`LEN_BITS-1:0] ALEN;
42			`output [1:0] ASIZE;`
43			`output AVALID;`
44			`input AREADY;`
45			`input AWVALID;`
46			`output AJOINT;`
47
48			`output [2:0] axim_timeout_num;`
49			`output axim_timeout;`
50
51
52
53			reg [`CMD_BITS-1:0] AID;
54			reg [`CMD_BITS-1:0] AID_reg;
55			`reg [32-1:0] AADDR;`
56			`reg APORT;`
57			reg [`LEN_BITS-1:0] ALEN;
58			`reg [1:0] ASIZE;`
59			`reg AVALID_reg;`
60			`reg AJOINT;`
61
62
63			wire [`CMD_BITS-1:0] AID_pre;
64			`wire [32-1:0] AADDR_pre;`
65			`wire [1:0] ASIZE_pre;`
66			wire [`LEN_BITS-1:0] ALEN_pre;
67			`wire [8-1:0] burst_length;`
68
69			`wire cmd;`
70			`reg cmd_pending;`
71			`wire cmd_line_pre;`
72			`wire cmd_line;`
73
74			`wire high_addr_pre;`
75			`wire high_addr;`
76			`wire [8:0] burst_reach_pre;`
77			`reg [8:0] burst_reach;`
78			`reg joint_cross;`
79			`wire page_cross_pre;`
80			`wire page_cross;`
81			`wire cross_start;`
82			`wire cross_start_d;`
83			`wire [8:0] max_burst;`
84			`reg [8:0] max_burst_d;`
85			`reg next_burst;`
86			`reg [8-1:0] next_burst_size;`
87			`wire next_burst_start;`
88
89
90
91
92			`assign high_addr_pre = burst_addr[11:8] == 4'hf;`
93			`assign burst_reach_pre = burst_addr[7:0] + burst_size;`
94			`assign page_cross = high_addr & (burst_reach > {1'b1, {8{1'b0}}});`
95			`assign max_burst = {1'b1, {8{1'b0}}} - burst_addr[7:0];`
96			`assign next_burst_start = next_burst & (~AVALID_reg) & (~cmd_full);`
97			`assign cross_start = burst_start & page_cross;`
98
99
100			`prgen_delay #(1) delay_high_addr (.clk(clk), .reset(reset), .din(high_addr_pre), .dout(high_addr));`
101			`prgen_delay #(1) delay_cross_start (.clk(clk), .reset(reset), .din(cross_start), .dout(cross_start_d));`
102
103
104			`always @(posedge clk or posedge reset)`
105			`if (reset)`
106			`burst_reach <= #1 {9{1'b0}};`
107			`else if (high_addr_pre)`
108			`burst_reach <= #1 burst_reach_pre;`
109
110			`always @(posedge clk or posedge reset)`
111			`if (reset)`
112			`next_burst <= #1 1'b0;`
113			`else if (next_burst_start)`
114			`next_burst <= #1 1'b0;`
115			`else if (cross_start)`
116			`next_burst <= #1 1'b1;`
117
118			`always @(posedge clk or posedge reset)`
119			`if (reset)`
120			`max_burst_d <= #1 {9{1'b0}};`
121			`else if (cross_start)`
122			`max_burst_d <= #1 max_burst;`
123
124			`always @(posedge clk or posedge reset)`
125			`if (reset)`
126			`next_burst_size <= #1 {8{1'b0}};`
127			`else if (cross_start)`
128			`next_burst_size <= #1 burst_size;`
129			`else if (cross_start_d)`
130			`next_burst_size <= #1 next_burst_size - max_burst_d;`
131
132			`assign cmd_split = cross_start_d;`
133
134			`assign cmd = AVALID & AREADY;`
135			`assign cmd_num = AID[2:0];`
136			`assign cmd_line_pre = cmd & AID[6];`
137
138			`assign joint_pending = AVALID & (~AREADY) & AJOINT;`
139
140			`always @(posedge clk or posedge reset)`
141			`if (reset)`
142			`cmd_pending <= #1 1'b0;`
143			`else if (burst_start)`
144			`cmd_pending <= #1 1'b1;`
145			`else if (cmd & (~next_burst))`
146			`cmd_pending <= #1 1'b0;`
147
148
149			`prgen_delay #(1) delay_cmd_line (.clk(clk), .reset(reset), .din(cmd_line_pre), .dout(cmd_line));`
150
151			`assign AID_pre = {`
152			`end_line_cmd, //[6]`
153			`ASIZE_pre[1:0], //[5:4]`
154			`extra_bit, //[3]`
155			`ch_num[2:0] //[2:0]`
156			`};`
157
158			`assign AADDR_pre = burst_addr;`
159
160			`assign ASIZE_pre =`
161			`burst_size == 'd1 ? 2'b00 :`
162			`burst_size == 'd2 ? 2'b01 :`
163			`burst_size == 'd4 ? 2'b10 :`
164			`AXI_WORD_SIZE;`
165
166			`assign burst_length =`
167			`next_burst ? next_burst_size :`
168			`page_cross ? max_burst : burst_size;`
169
170			`assign ALEN_pre =`
171			burst_length[8-1:AXI_3] == 'd0 ? {`LEN_BITS{1'b0}} :
172			`burst_length[8-1:AXI_3] - 1'b1;`
173
174
175			`always @(posedge clk or posedge reset)`
176			`if (reset)`
177			`begin`
178			`ASIZE <= #1 {2{1'b0}};`
179			`AJOINT <= #1 1'b0;`
180			`end`
181			`else if (burst_start)`
182			`begin`
183			`ASIZE <= #1 ASIZE_pre;`
184			`AJOINT <= #1 joint_req;`
185			`end`
186
187			`always @(posedge clk or posedge reset)`
188			`if (reset)`
189			AID_reg <= #1 {`CMD_BITS{1'b0}};
190			`else if (burst_start)`
191			`AID_reg <= #1 AID_pre;`
192
193			`always @(AID_reg or next_burst)`
194			`begin`
195			`AID = AID_reg;`
196			AID[`ID_END_LINE] = AID_reg[`ID_END_LINE] & (~next_burst);
197			AID[`ID_LAST] = AID_reg[`ID_LAST] & (~next_burst);
198			`end`
199
200			`always @(posedge clk or posedge reset)`
201			`if (reset)`
202			`AADDR <= #1 {32{1'b0}};`
203			`else if (next_burst_start)`
204			`AADDR <= #1 {AADDR[32-1:12], {12{1'b1}}} + 1'b1;`
205			`else if (burst_start)`
206			`AADDR <= #1 AADDR_pre;`
207
208			`always @(posedge clk or posedge reset)`
209			`if (reset)`
210			`APORT <= #1 1'b0;`
211			`else if (burst_start)`
212			`APORT <= #1 cmd_port;`
213
214			`always @(posedge clk or posedge reset)`
215			`if (reset)`
216			ALEN <= #1 {`LEN_BITS{1'b0}};
217			`else if (burst_start \| next_burst_start)`
218			`ALEN <= #1 ALEN_pre;`
219
220			`always @(posedge clk or posedge reset)`
221			`if (reset)`
222			`AVALID_reg <= #1 1'b0;`
223			`else if (AVALID & AREADY)`
224			`AVALID_reg <= #1 1'b0;`
225			`else if ((burst_start & (burst_size > 'd0)) \| next_burst_start)`
226			`AVALID_reg <= #1 1'b1;`
227
228			`assign AVALID = AJOINT ? AVALID_reg & (~AWVALID) : AVALID_reg;`
229
230			`dma_axi64_core0_axim_timeout dma_axi64_axim_timeout (`
231			`.clk(clk),`
232			`.reset(reset),`
233			`.VALID(AVALID),`
234			`.READY(AREADY),`
235			`.ID(AID),`
236			`.axim_timeout_num(axim_timeout_num),`
237			`.axim_timeout(axim_timeout)`
238			`);`
239
240
241			`endmodule`
242
243
244
245
246