Subversion Repositories dma_axi

//---------------------------------------------------------

//-- File generated by RobustVerilog parser

//-- Version: 1.0

//-- Invoked Fri Mar 25 23:36:57 2011

//--

//-- Source file: dma_ch_fifo.v

//---------------------------------------------------------

module dma_axi64_core0_ch_fifo (CLK,WR,RD,WR_ADDR,RD_ADDR,DIN,BSEL,DOUT);

   input                      CLK;

   input               WR;

   input               RD;

   input [5-3-1:0] WR_ADDR;

   input [5-3-1:0] RD_ADDR;

   input [64-1:0]      DIN;

   input [8-1:0]      BSEL;

   output [64-1:0]     DOUT;

   reg [64-1:0]           Mem [4-1:0];

   wire [64-1:0]       BitSEL;

   wire [64-1:0]       DIN_BitSEL;

   reg [64-1:0]           DOUT;

     assign               BitSEL = {{8{BSEL[7]}} , {8{BSEL[6]}} , {8{BSEL[5]}} , {8{BSEL[4]}} , {8{BSEL[3]}} , {8{BSEL[2]}} , {8{BSEL[1]}} , {8{BSEL[0]}}};

   assign               DIN_BitSEL = (Mem[WR_ADDR] & ~BitSEL) | (DIN & BitSEL);

   always @(posedge CLK)

     if (WR)

       Mem[WR_ADDR] <= #1 DIN_BitSEL;

   always @(posedge CLK)

     if (RD)

       DOUT <= #1 Mem[RD_ADDR];

endmodule