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[/] [dma_axi/] [trunk/] [src/] [dma_axi64/] [dma_axi64_defines.v] - Blame information for rev 2

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//---------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- Version: 1.0
//-- Invoked Fri Mar 25 23:36:53 2011
//--
//-- Source file: dma_defines.v
//---------------------------------------------------------
 
 
 
`define FRAME_BITS     12
`define X_BITS         8
`define TOKEN_BITS     6
`define OUT_BITS       4
`define DELAY_BITS     3
`define CMD_CNT_BITS   12
`define INT_CNT_BITS   4
`define WAIT_BITS      12
`define TIMEOUT_BITS   10
`define WDT_BITS       11
`define CMD_BITS       7
`define ID_BITS        1
`define LEN_BITS       4
`define SIZE_BITS      2
 
`define ID_END_LINE    6
`define ID_LAST        3
 
 
 
 

Line No.	Rev	Author	Line
1	2	eyalhoc	`//---------------------------------------------------------`
2			`//-- File generated by RobustVerilog parser`
3			`//-- Version: 1.0`
4			`//-- Invoked Fri Mar 25 23:36:53 2011`
5			`//--`
6			`//-- Source file: dma_defines.v`
7			`//---------------------------------------------------------`
8
9
10
11			`define FRAME_BITS 12
12			`define X_BITS 8
13			`define TOKEN_BITS 6
14			`define OUT_BITS 4
15			`define DELAY_BITS 3
16			`define CMD_CNT_BITS 12
17			`define INT_CNT_BITS 4
18			`define WAIT_BITS 12
19			`define TIMEOUT_BITS 10
20			`define WDT_BITS 11
21			`define CMD_BITS 7
22			`define ID_BITS 1
23			`define LEN_BITS 4
24			`define SIZE_BITS 2
25
26			`define ID_END_LINE 6
27			`define ID_LAST 3
28
29
30
31

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[/] [dma_axi/] [trunk/] [src/] [dma_axi64/] [dma_axi64_defines.v] - Blame information for rev 2