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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2017
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib, common_components_lib, dp_pkg_lib;
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USE IEEE.std_logic_1164.all;
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USE common_pkg_lib.common_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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-- Author: Eric Kooistra, 17 nov 2017
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-- Purpose:
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-- Restore global BSN.
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-- Description:
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-- The input global BSN is active at the sync. In between sync the other BSN
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-- BSN at the sop may count a local BSN that restarted at 0 for every sync.
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-- This dp_bsn_restore_global takes the BSN at the sync and starts counting
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-- from there for every sop, so in this way it restores the global BSN count
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-- for the blocks in between syncs.
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-- The increment for each restored BSN is 1. The assumption is that the
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-- number of blocks between syncs equals the difference in global BSN values
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-- between syncs. In this way the restored BSN counts without gaps or
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-- duplicates.
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-- Remarks:
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ENTITY dp_bsn_restore_global IS
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GENERIC (
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g_bsn_w : NATURAL := c_dp_stream_bsn_w;
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g_pipeline : NATURAL := 1 -- 0 for wires, > 0 for registers
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);
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PORT (
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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-- ST sink
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snk_out : OUT t_dp_siso;
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snk_in : IN t_dp_sosi;
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-- ST source
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src_in : IN t_dp_siso := c_dp_siso_rdy;
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src_out : OUT t_dp_sosi
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);
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END dp_bsn_restore_global;
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ARCHITECTURE str OF dp_bsn_restore_global IS
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SIGNAL blk_sync : STD_LOGIC;
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SIGNAL bsn_at_sync : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
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SIGNAL nxt_bsn_at_sync : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
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SIGNAL bsn_restored : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
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SIGNAL snk_in_restored : t_dp_sosi;
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BEGIN
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-- keep BSN at sync
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p_clk : PROCESS(clk, rst)
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BEGIN
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IF rst='1' THEN
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bsn_at_sync <= (OTHERS=>'0');
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ELSIF rising_edge(clk) THEN
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bsn_at_sync <= nxt_bsn_at_sync;
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END IF;
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END PROCESS;
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-- Store global BSN at sync
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nxt_bsn_at_sync <= snk_in.bsn(g_bsn_w-1 DOWNTO 0) WHEN snk_in.sync='1' ELSE bsn_at_sync;
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-- Create block sync from snk_in.sync, this blk_sync is active during entire first sop-eop block of sync interval
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u_common_switch : ENTITY common_components_lib.common_switch
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GENERIC MAP (
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g_rst_level => '0', -- Defines the output level at reset.
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g_priority_lo => FALSE, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
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g_or_high => TRUE, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
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g_and_low => FALSE -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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switch_high => snk_in.sync, -- A pulse on switch_high makes the out_level go high
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switch_low => snk_in.eop, -- A pulse on switch_low makes the out_level go low
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out_level => blk_sync
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);
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-- Use stored global BSN at sync and add local BSN to restore the global BSN for every next sop
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bsn_restored <= snk_in.bsn WHEN blk_sync='1' ELSE ADD_UVEC(bsn_at_sync, snk_in.bsn, g_bsn_w);
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snk_in_restored <= func_dp_stream_bsn_set(snk_in, bsn_restored);
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-- Add pipeline to ensure timing closure for the restored BSN summation
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u_pipeline : ENTITY work.dp_pipeline
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GENERIC MAP (
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g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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-- ST sink
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snk_out => snk_out,
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snk_in => snk_in_restored,
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-- ST source
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src_in => src_in,
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src_out => src_out
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);
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END str;
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