OpenCores
URL https://opencores.org/ocsvn/dp_components/dp_components/trunk

Subversion Repositories dp_components

[/] [dp_components/] [trunk/] [dp_hold_ctrl.vhd] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 danv
-------------------------------------------------------------------------------
2
--
3 4 danv
-- Copyright 2020
4 2 danv
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
5
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
6 4 danv
-- 
7
-- Licensed under the Apache License, Version 2.0 (the "License");
8
-- you may not use this file except in compliance with the License.
9
-- You may obtain a copy of the License at
10
-- 
11
--     http://www.apache.org/licenses/LICENSE-2.0
12
-- 
13
-- Unless required by applicable law or agreed to in writing, software
14
-- distributed under the License is distributed on an "AS IS" BASIS,
15
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16
-- See the License for the specific language governing permissions and
17
-- limitations under the License.
18 2 danv
--
19
-------------------------------------------------------------------------------
20
 
21
LIBRARY IEEE, common_components_lib;
22
USE IEEE.std_logic_1164.all;
23
 
24
-- Purpose:
25
--   Hold hld_ctrl active until next ready high when in_ctrl is active while
26
--   ready went low
27
-- Description:
28
--   When ready goes low there may still arrive one new valid data. The control
29
--   information for this data can then be held with this component. When ready
30
--   goes high again the held data can then be output and the hld_ctrl is 
31
--   released. After that the subsequent data output can come directly from the
32
--   up stream source, until ready goes low again.
33
-- Remarks:
34
-- . Ready latency RL = 1
35
-- . The in_ctrl is typically in_valid, in_sop or in_eop
36
-- . Typically used together with dp_hold_data
37
 
38
ENTITY dp_hold_ctrl IS
39
  PORT (
40
    rst      : IN  STD_LOGIC;
41
    clk      : IN  STD_LOGIC;
42
    ready    : IN  STD_LOGIC;
43
    in_ctrl  : IN  STD_LOGIC;
44
    hld_ctrl : OUT STD_LOGIC
45
  );
46
END dp_hold_ctrl;
47
 
48
 
49
ARCHITECTURE rtl OF dp_hold_ctrl IS
50
 
51
  SIGNAL hi_ctrl : STD_LOGIC;
52
  SIGNAL lo_ctrl : STD_LOGIC;
53
 
54
BEGIN
55
 
56
  hi_ctrl <=     in_ctrl AND NOT ready;  -- capture
57
  lo_ctrl <= NOT in_ctrl AND     ready;  -- release
58
 
59
  u_hld_ctrl : ENTITY common_components_lib.common_switch
60
  PORT MAP (
61
    rst         => rst,
62
    clk         => clk,
63
    switch_high => hi_ctrl,
64
    switch_low  => lo_ctrl,
65
    out_level   => hld_ctrl
66
  );
67
 
68
END rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.