URL https://opencores.org/ocsvn/dp_components/dp_components/trunk

Subversion Repositories dp_components

[/] [dp_components/] [trunk/] [hdllib.cfg] - Blame information for rev 5

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hdl_lib_name = dp_components
hdl_library_clause_name = dp_components_lib
hdl_lib_uses_synth = common_pkg common_components dp_pkg
hdl_lib_uses_sim =
hdl_lib_technology =
 
synth_files =
    dp_latency_increase.vhd
    dp_latency_adapter.vhd
    dp_hold_ctrl.vhd
    dp_hold_input.vhd
    dp_xonoff.vhd
    dp_block_gen.vhd
 
test_bench_files =
    tb_dp_latency_adapter.vhd
 
regression_test_vhdl =
    tb_dp_latency_adapter.vhd
 
[modelsim_project_file]
 
 
[quartus_project_file]

Line No.	Rev	Author	Line
1	2	danv	`hdl_lib_name = dp_components`
2			`hdl_library_clause_name = dp_components_lib`
3			`hdl_lib_uses_synth = common_pkg common_components dp_pkg`
4			`hdl_lib_uses_sim =`
5			`hdl_lib_technology =`
6
7			`synth_files =`
8			`dp_latency_increase.vhd`
9			`dp_latency_adapter.vhd`
10			`dp_hold_ctrl.vhd`
11			`dp_hold_input.vhd`
12	3	danv	`dp_xonoff.vhd`
13	5	danv	`dp_block_gen.vhd`
14	2	danv
15			`test_bench_files =`
16			`tb_dp_latency_adapter.vhd`
17
18			`regression_test_vhdl =`
19			`tb_dp_latency_adapter.vhd`
20
21			`[modelsim_project_file]`
22
23
24			`[quartus_project_file]`

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Subversion Repositories dp_components

[/] [dp_components/] [trunk/] [hdllib.cfg] - Blame information for rev 5