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[/] [dpll-isdn/] [trunk/] [Sources/] [randomwalkfilter.v] - Blame information for rev 2

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1 2 dmsu
 
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/* Random Walk Filter with reset value of 0*/
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module randomwalkfilter(MainClock, Lead, Lag, Positive, Negative);
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 input  MainClock, Lead, Lag;    // System Clock and Phase Comparator signals
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 output Positive, Negative;      // "positive shift" and "negative shift" outputs
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/* some parametere are accessible from outside */
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parameter FilterLength      = 8;
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parameter FilterResetValue  = 4;
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parameter FilterMaxValue    = FilterResetValue;
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parameter FilterMinValue    = 256 - FilterResetValue;
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/* reversive counter */
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reg [FilterLength-1 : 0] FilterCounter;
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/* calculation of output pulses synchrinized with MainClock */
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always @(posedge MainClock)
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 begin
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  if((FilterCounter == FilterMaxValue) || (FilterCounter == FilterMinValue))
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    FilterCounter <= 0;
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    else
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     begin
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      if(Lead) FilterCounter <= FilterCounter + 1;
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      if(Lag)  FilterCounter <= FilterCounter - 1;
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     end
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 end
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/* making "Lead" and "Lag" signals when  */
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/* counter reached max or min levels     */
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reg Positive, Negative;
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always @(posedge MainClock)
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 begin
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  Positive <= (FilterCounter == FilterMaxValue);
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  Negative <= (FilterCounter == FilterMinValue);
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 end
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endmodule
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