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1 7 akhachat 
// *******************************************************************************************************
2 
// **                                                                                                   **
3 
// **   24LC16B.v - Microchip 24LC16B 16K-BIT I2C SERIAL EEPROM (VCC = +2.5V TO +5.5V)                  **
4 
// **                                                                                                   **
5 
// *******************************************************************************************************
6 
// **                                                                                                   **
7 
// **                   This information is distributed under license from Young Engineering.           **
8 
// **                              COPYRIGHT (c) 2003 YOUNG ENGINEERING                                 **
9 
// **                                      ALL RIGHTS RESERVED                                          **
10 
// **                                                                                                   **
11 
// **                                                                                                   **
12 
// **   Young Engineering provides design expertise for the digital world                               **
13 
// **   Started in 1990, Young Engineering offers products and services for your electronic design      **
14 
// **   project.  We have the expertise in PCB, FPGA, ASIC, firmware, and software design.              **
15 
// **   From concept to prototype to production, we can help you.                                       **
16 
// **                                                                                                   **
17 
// **   http://www.young-engineering.com/                                                               **
18 
// **                                                                                                   **
19 
// *******************************************************************************************************
20 
// **   This information is provided to you for your convenience and use with Microchip products only.  **
21 
// **   Microchip disclaims all liability arising from this information and its use.                    **
22 
// **                                                                                                   **
23 
// **   THIS INFORMATION IS PROVIDED "AS IS." MICROCHIP MAKES NO REPRESENTATION OR WARRANTIES OF        **
24 
// **   ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO        **
25 
// **   THE INFORMATION PROVIDED TO YOU, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY,           **
26 
// **   PERFORMANCE, MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR PURPOSE.                         **
27 
// **   MICROCHIP IS NOT LIABLE, UNDER ANY CIRCUMSTANCES, FOR SPECIAL, INCIDENTAL OR CONSEQUENTIAL      **
28 
// **   DAMAGES, FOR ANY REASON WHATSOEVER.                                                             **
29 
// **                                                                                                   **
30 
// **   It is your responsibility to ensure that your application meets with your specifications.       **
31 
// **                                                                                                   **
32 
// *******************************************************************************************************
33 
// **   Revision       : 1.0                                                                            **
34 
// **   Modified Date  : 12/04/2006                                                                     **
35 
// **   Revision History:                                                                               **
36 
// **                                                                                                   **
37 
// **   12/04/2006:  Initial design                                                                     **
38 
// **                                                                                                   **
39 
// *******************************************************************************************************
40 
// **                                       TABLE OF CONTENTS                                           **
41 
// *******************************************************************************************************
42 
// **---------------------------------------------------------------------------------------------------**
43 
// **   DECLARATIONS                                                                                    **
44 
// **---------------------------------------------------------------------------------------------------**
45 
// **---------------------------------------------------------------------------------------------------**
46 
// **   INITIALIZATION                                                                                  **
47 
// **---------------------------------------------------------------------------------------------------**
48 
// **---------------------------------------------------------------------------------------------------**
49 
// **   CORE LOGIC                                                                                      **
50 
// **---------------------------------------------------------------------------------------------------**
51 
// **   1.01:  START Bit Detection                                                                      **
52 
// **   1.02:  STOP Bit Detection                                                                       **
53 
// **   1.03:  Input Shift Register                                                                     **
54 
// **   1.04:  Input Bit Counter                                                                        **
55 
// **   1.05:  Control Byte Register                                                                    **
56 
// **   1.06:  Byte Address Register                                                                    **
57 
// **   1.07:  Write Data Buffer                                                                        **
58 
// **   1.08:  Acknowledge Generator                                                                    **
59 
// **   1.09:  Acknowledge Detect                                                                       **
60 
// **   1.10:  Write Cycle Timer                                                                        **
61 
// **   1.11:  Write Cycle Processor                                                                    **
62 
// **   1.12:  Read Data Multiplexor                                                                    **
63 
// **   1.13:  Read Data Processor                                                                      **
64 
// **   1.14:  SDA Data I/O Buffer                                                                      **
65 
// **                                                                                                   **
66 
// **---------------------------------------------------------------------------------------------------**
67 
// **   DEBUG LOGIC                                                                                     **
68 
// **---------------------------------------------------------------------------------------------------**
69 
// **   2.01:  Memory Data Bytes                                                                        **
70 
// **   2.02:  Write Data Buffer                                                                        **
71 
// **                                                                                                   **
72 
// **---------------------------------------------------------------------------------------------------**
73 
// **   TIMING CHECKS                                                                                   **
74 
// **---------------------------------------------------------------------------------------------------**
75 
// **                                                                                                   **
76 
// *******************************************************************************************************
77 
 
78 
 
79 
`timescale 1ns/10ps
80 
 
81 
module M24LC16B (A0, A1, A2, WP, SDA, SCL, RESET);
82 
 
83 
   input                A0;                             // unconnected pin
84 
   input                A1;                             // unconnected pin
85 
   input                A2;                             // unconnected pin
86 
 
87 
   input                WP;                             // write protect pin
88 
 
89 
   inout                SDA;                            // serial data I/O
90 
   input                SCL;                            // serial data clock
91 
 
92 
   input                RESET;                          // system reset
93 
 
94 
 
95 
// *******************************************************************************************************
96 
// **   DECLARATIONS                                                                                    **
97 
// *******************************************************************************************************
98 
 
99 
   reg                  SDA_DO;                         // serial data - output
100 
   reg                  SDA_OE;                         // serial data - output enable
101 
 
102 
   wire                 SDA_DriveEnable;                // serial data output enable
103 
   reg                  SDA_DriveEnableDlyd;            // serial data output enable - delayed
104 
 
105 
   reg  [03:00]         BitCounter;                     // serial bit counter
106 
 
107 
   reg                  START_Rcvd;                     // START bit received flag
108 
   reg                  STOP_Rcvd;                      // STOP bit received flag
109 
   reg                  CTRL_Rcvd;                      // control byte received flag
110 
   reg                  ADDR_Rcvd;                      // byte address received flag
111 
   reg                  MACK_Rcvd;                      // master acknowledge received flag
112 
 
113 
   reg                  WrCycle;                        // memory write cycle
114 
   reg                  RdCycle;                        // memory read cycle
115 
 
116 
   reg  [07:00]         ShiftRegister;                  // input data shift register
117 
 
118 
   reg  [07:00]         ControlByte;                    // control byte register
119 
   wire [02:00]         BlockSelect;                    // memory block select
120 
   wire                 RdWrBit;                        // read/write control bit
121 
 
122 
   reg  [10:00]         StartAddress;                   // memory access starting address
123 
   reg  [03:00]         PageAddress;                    // memory page address
124 
 
125 
   reg  [07:00]         WrDataByte [0:15];               // memory write data buffer
126 
   wire [07:00]         RdDataByte;                     // memory read data
127 
 
128 
   reg  [15:00]         WrCounter;                      // write buffer counter
129 
 
130 
   reg  [03:00]         WrPointer;                      // write buffer pointer
131 
   reg  [10:00]         RdPointer;                      // read address pointer
132 
 
133 
   reg                  WriteActive;                    // memory write cycle active
134 
 
135 
   reg  [07:00]         MemoryBlock0 [0:255];            // EEPROM data memory array
136 
   reg  [07:00]         MemoryBlock1 [0:255];            // EEPROM data memory array
137 
   reg  [07:00]         MemoryBlock2 [0:255];            // EEPROM data memory array
138 
   reg  [07:00]         MemoryBlock3 [0:255];            // EEPROM data memory array
139 
   reg  [07:00]         MemoryBlock4 [0:255];            // EEPROM data memory array
140 
   reg  [07:00]         MemoryBlock5 [0:255];            // EEPROM data memory array
141 
   reg  [07:00]         MemoryBlock6 [0:255];            // EEPROM data memory array
142 
   reg  [07:00]         MemoryBlock7 [0:255];            // EEPROM data memory array
143 
 
144 
   integer              LoopIndex;                      // iterative loop index
145 
 
146 
   integer              tAA;                            // timing parameter
147 
   integer              tWC;                            // timing parameter
148 
 
149 
 
150 
// *******************************************************************************************************
151 
// **   INITIALIZATION                                                                                  **
152 
// *******************************************************************************************************
153 
 
154 
   initial tAA = 900;                                   // SCL to SDA output delay
155 
   initial tWC = 5000000;                               // memory write cycle time
156 
 
157 
   initial begin
158 
      SDA_DO = 0;
159 
      SDA_OE = 0;
160 
   end
161 
 
162 
   initial begin
163 
      START_Rcvd = 0;
164 
      STOP_Rcvd  = 0;
165 
      CTRL_Rcvd  = 0;
166 
      ADDR_Rcvd  = 0;
167 
      MACK_Rcvd  = 0;
168 
   end
169 
 
170 
   initial begin
171 
      BitCounter  = 0;
172 
      ControlByte = 0;
173 
   end
174 
 
175 
   initial begin
176 
      WrCycle = 0;
177 
      RdCycle = 0;
178 
 
179 
      WriteActive = 0;
180 
   end
181 
 
182 
 
183 
// *******************************************************************************************************
184 
// **   CORE LOGIC                                                                                      **
185 
// *******************************************************************************************************
186 
// -------------------------------------------------------------------------------------------------------
187 
//      1.01:  START Bit Detection
188 
// -------------------------------------------------------------------------------------------------------
189 
 
190 
   always @(negedge SDA) begin
191 
      if (SCL == 1) begin
192 
         START_Rcvd <= 1;
193 
         STOP_Rcvd  <= 0;
194 
         CTRL_Rcvd  <= 0;
195 
         ADDR_Rcvd  <= 0;
196 
         MACK_Rcvd  <= 0;
197 
 
198 
         WrCycle <= #1 0;
199 
         RdCycle <= #1 0;
200 
 
201 
         BitCounter <= 0;
202 
      end
203 
   end
204 
 
205 
// -------------------------------------------------------------------------------------------------------
206 
//      1.02:  STOP Bit Detection
207 
// -------------------------------------------------------------------------------------------------------
208 
 
209 
   always @(posedge SDA) begin
210 
      if (SCL == 1) begin
211 
         START_Rcvd <= 0;
212 
         STOP_Rcvd  <= 1;
213 
         CTRL_Rcvd  <= 0;
214 
         ADDR_Rcvd  <= 0;
215 
         MACK_Rcvd  <= 0;
216 
 
217 
         WrCycle <= #1 0;
218 
         RdCycle <= #1 0;
219 
 
220 
         BitCounter <= 10;
221 
      end
222 
   end
223 
 
224 
// -------------------------------------------------------------------------------------------------------
225 
//      1.03:  Input Shift Register
226 
// -------------------------------------------------------------------------------------------------------
227 
 
228 
   always @(posedge SCL) begin
229 
      ShiftRegister[00] <= SDA;
230 
      ShiftRegister[01] <= ShiftRegister[00];
231 
      ShiftRegister[02] <= ShiftRegister[01];
232 
      ShiftRegister[03] <= ShiftRegister[02];
233 
      ShiftRegister[04] <= ShiftRegister[03];
234 
      ShiftRegister[05] <= ShiftRegister[04];
235 
      ShiftRegister[06] <= ShiftRegister[05];
236 
      ShiftRegister[07] <= ShiftRegister[06];
237 
   end
238 
 
239 
// -------------------------------------------------------------------------------------------------------
240 
//      1.04:  Input Bit Counter
241 
// -------------------------------------------------------------------------------------------------------
242 
 
243 
   always @(posedge SCL) begin
244 
      if (BitCounter < 10) BitCounter <= BitCounter + 1;
245 
   end
246 
 
247 
// -------------------------------------------------------------------------------------------------------
248 
//      1.05:  Control Byte Register
249 
// -------------------------------------------------------------------------------------------------------
250 
 
251 
   always @(negedge SCL) begin
252 
      if (START_Rcvd & (BitCounter == 8)) begin
253 
         if (!WriteActive & (ShiftRegister[07:04] == 4'b1010)) begin
254 
            if (ShiftRegister[00] == 0) WrCycle <= 1;
255 
            if (ShiftRegister[00] == 1) RdCycle <= 1;
256 
 
257 
            ControlByte <= ShiftRegister[07:00];
258 
 
259 
            CTRL_Rcvd <= 1;
260 
         end
261 
 
262 
         START_Rcvd <= 0;
263 
      end
264 
   end
265 
 
266 
   assign BlockSelect = ControlByte[03:01];
267 
   assign RdWrBit     = ControlByte[00];
268 
 
269 
// -------------------------------------------------------------------------------------------------------
270 
//      1.06:  Byte Address Register
271 
// -------------------------------------------------------------------------------------------------------
272 
 
273 
   always @(negedge SCL) begin
274 
      if (CTRL_Rcvd & (BitCounter == 8)) begin
275 
         if (RdWrBit == 0) begin
276 
            StartAddress <= {BlockSelect[02:00],ShiftRegister[07:00]};
277 
            RdPointer    <= {BlockSelect[02:00],ShiftRegister[07:00]};
278 
 
279 
            ADDR_Rcvd <= 1;
280 
         end
281 
 
282 
         WrCounter <= 0;
283 
         WrPointer <= 0;
284 
 
285 
         CTRL_Rcvd <= 0;
286 
      end
287 
   end
288 
 
289 
// -------------------------------------------------------------------------------------------------------
290 
//      1.07:  Write Data Buffer
291 
// -------------------------------------------------------------------------------------------------------
292 
 
293 
   always @(negedge SCL) begin
294 
      if (ADDR_Rcvd & (BitCounter == 8)) begin
295 
         if ((WP == 0) & (RdWrBit == 0)) begin
296 
            WrDataByte[WrPointer] <= ShiftRegister[07:00];
297 
 
298 
            WrCounter <= WrCounter + 1;
299 
            WrPointer <= WrPointer + 1;
300 
         end
301 
      end
302 
   end
303 
 
304 
// -------------------------------------------------------------------------------------------------------
305 
//      1.08:  Acknowledge Generator
306 
// -------------------------------------------------------------------------------------------------------
307 
 
308 
   always @(negedge SCL) begin
309 
      if (!WriteActive) begin
310 
         if (BitCounter == 8) begin
311 
            if (WrCycle | (START_Rcvd & (ShiftRegister[07:04] == 4'b1010))) begin
312 
               SDA_DO <= 0;
313 
               SDA_OE <= 1;
314 
            end
315 
         end
316 
         if (BitCounter == 9) begin
317 
            BitCounter <= 0;
318 
 
319 
            if (!RdCycle) begin
320 
               SDA_DO <= 0;
321 
               SDA_OE <= 0;
322 
            end
323 
         end
324 
      end
325 
   end
326 
 
327 
// -------------------------------------------------------------------------------------------------------
328 
//      1.09:  Acknowledge Detect
329 
// -------------------------------------------------------------------------------------------------------
330 
 
331 
   always @(posedge SCL) begin
332 
      if (RdCycle & (BitCounter == 8)) begin
333 
         if ((SDA == 0) & (SDA_OE == 0)) MACK_Rcvd <= 1;
334 
      end
335 
   end
336 
 
337 
   always @(negedge SCL) MACK_Rcvd <= 0;
338 
 
339 
// -------------------------------------------------------------------------------------------------------
340 
//      1.10:  Write Cycle Timer
341 
// -------------------------------------------------------------------------------------------------------
342 
 
343 
   always @(posedge STOP_Rcvd) begin
344 
      if (WrCycle & (WP == 0) & (WrCounter > 0)) begin
345 
         WriteActive = 1;
346 
         #(tWC);
347 
         WriteActive = 0;
348 
      end
349 
   end
350 
 
351 
   always @(posedge STOP_Rcvd) begin
352 
      #(1.0);
353 
      STOP_Rcvd = 0;
354 
   end
355 
 
356 
// -------------------------------------------------------------------------------------------------------
357 
//      1.11:  Write Cycle Processor
358 
// -------------------------------------------------------------------------------------------------------
359 
 
360 
   always @(negedge WriteActive) begin
361 
      for (LoopIndex = 0; LoopIndex < WrCounter; LoopIndex = LoopIndex + 1) begin
362 
         PageAddress = StartAddress[03:00] + LoopIndex;
363 
 
364 
         case (StartAddress[10:08])
365 
            3'b000 : MemoryBlock0[{StartAddress[07:04],PageAddress[03:00]}] = WrDataByte[LoopIndex[03:00]];
366 
            3'b001 : MemoryBlock1[{StartAddress[07:04],PageAddress[03:00]}] = WrDataByte[LoopIndex[03:00]];
367 
            3'b010 : MemoryBlock2[{StartAddress[07:04],PageAddress[03:00]}] = WrDataByte[LoopIndex[03:00]];
368 
            3'b011 : MemoryBlock3[{StartAddress[07:04],PageAddress[03:00]}] = WrDataByte[LoopIndex[03:00]];
369 
            3'b100 : MemoryBlock4[{StartAddress[07:04],PageAddress[03:00]}] = WrDataByte[LoopIndex[03:00]];
370 
            3'b101 : MemoryBlock5[{StartAddress[07:04],PageAddress[03:00]}] = WrDataByte[LoopIndex[03:00]];
371 
            3'b110 : MemoryBlock6[{StartAddress[07:04],PageAddress[03:00]}] = WrDataByte[LoopIndex[03:00]];
372 
            3'b111 : MemoryBlock7[{StartAddress[07:04],PageAddress[03:00]}] = WrDataByte[LoopIndex[03:00]];
373 
         endcase
374 
      end
375 
   end
376 
 
377 
// -------------------------------------------------------------------------------------------------------
378 
//      1.12:  Read Data Multiplexor
379 
// -------------------------------------------------------------------------------------------------------
380 
 
381 
   always @(negedge SCL) begin
382 
      if (BitCounter == 8) begin
383 
         if (WrCycle & ADDR_Rcvd) begin
384 
            RdPointer <= StartAddress + WrPointer + 1;
385 
         end
386 
         if (RdCycle) begin
387 
            RdPointer <= RdPointer + 1;
388 
         end
389 
      end
390 
   end
391 
 
392 
   assign RdDataByte = {8{(RdPointer[10:08] == 0)}} & MemoryBlock0[RdPointer[07:00]]
393 
                     | {8{(RdPointer[10:08] == 1)}} & MemoryBlock1[RdPointer[07:00]]
394 
                     | {8{(RdPointer[10:08] == 2)}} & MemoryBlock2[RdPointer[07:00]]
395 
                     | {8{(RdPointer[10:08] == 3)}} & MemoryBlock3[RdPointer[07:00]]
396 
                     | {8{(RdPointer[10:08] == 4)}} & MemoryBlock4[RdPointer[07:00]]
397 
                     | {8{(RdPointer[10:08] == 5)}} & MemoryBlock5[RdPointer[07:00]]
398 
                     | {8{(RdPointer[10:08] == 6)}} & MemoryBlock6[RdPointer[07:00]]
399 
                     | {8{(RdPointer[10:08] == 7)}} & MemoryBlock7[RdPointer[07:00]];
400 
 
401 
// -------------------------------------------------------------------------------------------------------
402 
//      1.13:  Read Data Processor
403 
// -------------------------------------------------------------------------------------------------------
404 
 
405 
   always @(negedge SCL) begin
406 
      if (RdCycle) begin
407 
         if (BitCounter == 8) begin
408 
            SDA_DO <= 0;
409 
            SDA_OE <= 0;
410 
         end
411 
         else if (BitCounter == 9) begin
412 
            SDA_DO <= RdDataByte[07];
413 
 
414 
            if (MACK_Rcvd) SDA_OE <= 1;
415 
         end
416 
         else begin
417 
            SDA_DO <= RdDataByte[7-BitCounter];
418 
         end
419 
      end
420 
   end
421 
 
422 
// -------------------------------------------------------------------------------------------------------
423 
//      1.14:  SDA Data I/O Buffer
424 
// -------------------------------------------------------------------------------------------------------
425 
 
426 
   bufif1 (SDA, 1'b0, SDA_DriveEnableDlyd);
427 
 
428 
   assign SDA_DriveEnable = !SDA_DO & SDA_OE;
429 
   always @(SDA_DriveEnable) SDA_DriveEnableDlyd <= #(tAA) SDA_DriveEnable;
430 
 
431 
 
432 
// *******************************************************************************************************
433 
// **   DEBUG LOGIC                                                                                     **
434 
// *******************************************************************************************************
435 
// -------------------------------------------------------------------------------------------------------
436 
//      2.01:  Memory Data Bytes
437 
// -------------------------------------------------------------------------------------------------------
438 
 
439 
   wire [07:00] MemoryByte0_00 = MemoryBlock0[00];
440 
   wire [07:00] MemoryByte0_01 = MemoryBlock0[01];
441 
   wire [07:00] MemoryByte0_02 = MemoryBlock0[02];
442 
   wire [07:00] MemoryByte0_03 = MemoryBlock0[03];
443 
   wire [07:00] MemoryByte0_04 = MemoryBlock0[04];
444 
   wire [07:00] MemoryByte0_05 = MemoryBlock0[05];
445 
   wire [07:00] MemoryByte0_06 = MemoryBlock0[06];
446 
   wire [07:00] MemoryByte0_07 = MemoryBlock0[07];
447 
 
448 
   wire [07:00] MemoryByte0_08 = MemoryBlock0[08];
449 
   wire [07:00] MemoryByte0_09 = MemoryBlock0[09];
450 
   wire [07:00] MemoryByte0_0A = MemoryBlock0[10];
451 
   wire [07:00] MemoryByte0_0B = MemoryBlock0[11];
452 
   wire [07:00] MemoryByte0_0C = MemoryBlock0[12];
453 
   wire [07:00] MemoryByte0_0D = MemoryBlock0[13];
454 
   wire [07:00] MemoryByte0_0E = MemoryBlock0[14];
455 
   wire [07:00] MemoryByte0_0F = MemoryBlock0[15];
456 
 
457 
   wire [07:00] MemoryByte1_00 = MemoryBlock1[00];
458 
   wire [07:00] MemoryByte1_01 = MemoryBlock1[01];
459 
   wire [07:00] MemoryByte1_02 = MemoryBlock1[02];
460 
   wire [07:00] MemoryByte1_03 = MemoryBlock1[03];
461 
   wire [07:00] MemoryByte1_04 = MemoryBlock1[04];
462 
   wire [07:00] MemoryByte1_05 = MemoryBlock1[05];
463 
   wire [07:00] MemoryByte1_06 = MemoryBlock1[06];
464 
   wire [07:00] MemoryByte1_07 = MemoryBlock1[07];
465 
 
466 
   wire [07:00] MemoryByte1_08 = MemoryBlock1[08];
467 
   wire [07:00] MemoryByte1_09 = MemoryBlock1[09];
468 
   wire [07:00] MemoryByte1_0A = MemoryBlock1[10];
469 
   wire [07:00] MemoryByte1_0B = MemoryBlock1[11];
470 
   wire [07:00] MemoryByte1_0C = MemoryBlock1[12];
471 
   wire [07:00] MemoryByte1_0D = MemoryBlock1[13];
472 
   wire [07:00] MemoryByte1_0E = MemoryBlock1[14];
473 
   wire [07:00] MemoryByte1_0F = MemoryBlock1[15];
474 
 
475 
   wire [07:00] MemoryByte2_00 = MemoryBlock2[00];
476 
   wire [07:00] MemoryByte2_01 = MemoryBlock2[01];
477 
   wire [07:00] MemoryByte2_02 = MemoryBlock2[02];
478 
   wire [07:00] MemoryByte2_03 = MemoryBlock2[03];
479 
   wire [07:00] MemoryByte2_04 = MemoryBlock2[04];
480 
   wire [07:00] MemoryByte2_05 = MemoryBlock2[05];
481 
   wire [07:00] MemoryByte2_06 = MemoryBlock2[06];
482 
   wire [07:00] MemoryByte2_07 = MemoryBlock2[07];
483 
 
484 
   wire [07:00] MemoryByte2_08 = MemoryBlock2[08];
485 
   wire [07:00] MemoryByte2_09 = MemoryBlock2[09];
486 
   wire [07:00] MemoryByte2_0A = MemoryBlock2[10];
487 
   wire [07:00] MemoryByte2_0B = MemoryBlock2[11];
488 
   wire [07:00] MemoryByte2_0C = MemoryBlock2[12];
489 
   wire [07:00] MemoryByte2_0D = MemoryBlock2[13];
490 
   wire [07:00] MemoryByte2_0E = MemoryBlock2[14];
491 
   wire [07:00] MemoryByte2_0F = MemoryBlock2[15];
492 
 
493 
   wire [07:00] MemoryByte3_00 = MemoryBlock3[00];
494 
   wire [07:00] MemoryByte3_01 = MemoryBlock3[01];
495 
   wire [07:00] MemoryByte3_02 = MemoryBlock3[02];
496 
   wire [07:00] MemoryByte3_03 = MemoryBlock3[03];
497 
   wire [07:00] MemoryByte3_04 = MemoryBlock3[04];
498 
   wire [07:00] MemoryByte3_05 = MemoryBlock3[05];
499 
   wire [07:00] MemoryByte3_06 = MemoryBlock3[06];
500 
   wire [07:00] MemoryByte3_07 = MemoryBlock3[07];
501 
 
502 
   wire [07:00] MemoryByte3_08 = MemoryBlock3[08];
503 
   wire [07:00] MemoryByte3_09 = MemoryBlock3[09];
504 
   wire [07:00] MemoryByte3_0A = MemoryBlock3[10];
505 
   wire [07:00] MemoryByte3_0B = MemoryBlock3[11];
506 
   wire [07:00] MemoryByte3_0C = MemoryBlock3[12];
507 
   wire [07:00] MemoryByte3_0D = MemoryBlock3[13];
508 
   wire [07:00] MemoryByte3_0E = MemoryBlock3[14];
509 
   wire [07:00] MemoryByte3_0F = MemoryBlock3[15];
510 
 
511 
   wire [07:00] MemoryByte4_00 = MemoryBlock4[00];
512 
   wire [07:00] MemoryByte4_01 = MemoryBlock4[01];
513 
   wire [07:00] MemoryByte4_02 = MemoryBlock4[02];
514 
   wire [07:00] MemoryByte4_03 = MemoryBlock4[03];
515 
   wire [07:00] MemoryByte4_04 = MemoryBlock4[04];
516 
   wire [07:00] MemoryByte4_05 = MemoryBlock4[05];
517 
   wire [07:00] MemoryByte4_06 = MemoryBlock4[06];
518 
   wire [07:00] MemoryByte4_07 = MemoryBlock4[07];
519 
 
520 
   wire [07:00] MemoryByte4_08 = MemoryBlock4[08];
521 
   wire [07:00] MemoryByte4_09 = MemoryBlock4[09];
522 
   wire [07:00] MemoryByte4_0A = MemoryBlock4[10];
523 
   wire [07:00] MemoryByte4_0B = MemoryBlock4[11];
524 
   wire [07:00] MemoryByte4_0C = MemoryBlock4[12];
525 
   wire [07:00] MemoryByte4_0D = MemoryBlock4[13];
526 
   wire [07:00] MemoryByte4_0E = MemoryBlock4[14];
527 
   wire [07:00] MemoryByte4_0F = MemoryBlock4[15];
528 
 
529 
   wire [07:00] MemoryByte5_00 = MemoryBlock5[00];
530 
   wire [07:00] MemoryByte5_01 = MemoryBlock5[01];
531 
   wire [07:00] MemoryByte5_02 = MemoryBlock5[02];
532 
   wire [07:00] MemoryByte5_03 = MemoryBlock5[03];
533 
   wire [07:00] MemoryByte5_04 = MemoryBlock5[04];
534 
   wire [07:00] MemoryByte5_05 = MemoryBlock5[05];
535 
   wire [07:00] MemoryByte5_06 = MemoryBlock5[06];
536 
   wire [07:00] MemoryByte5_07 = MemoryBlock5[07];
537 
 
538 
   wire [07:00] MemoryByte5_08 = MemoryBlock5[08];
539 
   wire [07:00] MemoryByte5_09 = MemoryBlock5[09];
540 
   wire [07:00] MemoryByte5_0A = MemoryBlock5[10];
541 
   wire [07:00] MemoryByte5_0B = MemoryBlock5[11];
542 
   wire [07:00] MemoryByte5_0C = MemoryBlock5[12];
543 
   wire [07:00] MemoryByte5_0D = MemoryBlock5[13];
544 
   wire [07:00] MemoryByte5_0E = MemoryBlock5[14];
545 
   wire [07:00] MemoryByte5_0F = MemoryBlock5[15];
546 
 
547 
   wire [07:00] MemoryByte6_00 = MemoryBlock6[00];
548 
   wire [07:00] MemoryByte6_01 = MemoryBlock6[01];
549 
   wire [07:00] MemoryByte6_02 = MemoryBlock6[02];
550 
   wire [07:00] MemoryByte6_03 = MemoryBlock6[03];
551 
   wire [07:00] MemoryByte6_04 = MemoryBlock6[04];
552 
   wire [07:00] MemoryByte6_05 = MemoryBlock6[05];
553 
   wire [07:00] MemoryByte6_06 = MemoryBlock6[06];
554 
   wire [07:00] MemoryByte6_07 = MemoryBlock6[07];
555 
 
556 
   wire [07:00] MemoryByte6_08 = MemoryBlock6[08];
557 
   wire [07:00] MemoryByte6_09 = MemoryBlock6[09];
558 
   wire [07:00] MemoryByte6_0A = MemoryBlock6[10];
559 
   wire [07:00] MemoryByte6_0B = MemoryBlock6[11];
560 
   wire [07:00] MemoryByte6_0C = MemoryBlock6[12];
561 
   wire [07:00] MemoryByte6_0D = MemoryBlock6[13];
562 
   wire [07:00] MemoryByte6_0E = MemoryBlock6[14];
563 
   wire [07:00] MemoryByte6_0F = MemoryBlock6[15];
564 
 
565 
   wire [07:00] MemoryByte7_00 = MemoryBlock7[00];
566 
   wire [07:00] MemoryByte7_01 = MemoryBlock7[01];
567 
   wire [07:00] MemoryByte7_02 = MemoryBlock7[02];
568 
   wire [07:00] MemoryByte7_03 = MemoryBlock7[03];
569 
   wire [07:00] MemoryByte7_04 = MemoryBlock7[04];
570 
   wire [07:00] MemoryByte7_05 = MemoryBlock7[05];
571 
   wire [07:00] MemoryByte7_06 = MemoryBlock7[06];
572 
   wire [07:00] MemoryByte7_07 = MemoryBlock7[07];
573 
 
574 
   wire [07:00] MemoryByte7_08 = MemoryBlock7[08];
575 
   wire [07:00] MemoryByte7_09 = MemoryBlock7[09];
576 
   wire [07:00] MemoryByte7_0A = MemoryBlock7[10];
577 
   wire [07:00] MemoryByte7_0B = MemoryBlock7[11];
578 
   wire [07:00] MemoryByte7_0C = MemoryBlock7[12];
579 
   wire [07:00] MemoryByte7_0D = MemoryBlock7[13];
580 
   wire [07:00] MemoryByte7_0E = MemoryBlock7[14];
581 
   wire [07:00] MemoryByte7_0F = MemoryBlock7[15];
582 
 
583 
// -------------------------------------------------------------------------------------------------------
584 
//      2.02:  Write Data Buffer
585 
// -------------------------------------------------------------------------------------------------------
586 
 
587 
   wire [07:00] WriteData_0 = WrDataByte[00];
588 
   wire [07:00] WriteData_1 = WrDataByte[01];
589 
   wire [07:00] WriteData_2 = WrDataByte[02];
590 
   wire [07:00] WriteData_3 = WrDataByte[03];
591 
   wire [07:00] WriteData_4 = WrDataByte[04];
592 
   wire [07:00] WriteData_5 = WrDataByte[05];
593 
   wire [07:00] WriteData_6 = WrDataByte[06];
594 
   wire [07:00] WriteData_7 = WrDataByte[07];
595 
   wire [07:00] WriteData_8 = WrDataByte[08];
596 
   wire [07:00] WriteData_9 = WrDataByte[09];
597 
   wire [07:00] WriteData_A = WrDataByte[10];
598 
   wire [07:00] WriteData_B = WrDataByte[11];
599 
   wire [07:00] WriteData_C = WrDataByte[12];
600 
   wire [07:00] WriteData_D = WrDataByte[13];
601 
   wire [07:00] WriteData_E = WrDataByte[14];
602 
   wire [07:00] WriteData_F = WrDataByte[15];
603 
 
604 
 
605 
// *******************************************************************************************************
606 
// **   TIMING CHECKS                                                                                   **
607 
// *******************************************************************************************************
608 
 
609 
   wire TimingCheckEnable = (RESET == 0) & (SDA_OE == 0);
610 
 
611 
   specify
612 
      specparam
613 
         tHI = 600,                                     // SCL pulse width - high
614 
         tLO = 1300,                                    // SCL pulse width - low
615 
         tSU_STA = 600,                                 // SCL to SDA setup time
616 
         tHD_STA = 600,                                 // SCL to SDA hold time
617 
         tSU_DAT = 100,                                 // SDA to SCL setup time
618 
         tSU_STO = 600,                                 // SCL to SDA setup time
619 
         tBUF = 1300;                                   // Bus free time
620 
 
621 
      $width (posedge SCL, tHI);
622 
      $width (negedge SCL, tLO);
623 
 
624 
      $width (posedge SDA &&& SCL, tBUF);
625 
 
626 
      $setup (posedge SCL, negedge SDA &&& TimingCheckEnable, tSU_STA);
627 
      $setup (SDA, posedge SCL &&& TimingCheckEnable, tSU_DAT);
628 
      $setup (posedge SCL, posedge SDA &&& TimingCheckEnable, tSU_STO);
629 
 
630 
      $hold  (negedge SDA &&& TimingCheckEnable, negedge SCL, tHD_STA);
631 
   endspecify
632 
 
633 
endmodule

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